b441fd60b2
Preparation for developing a new rounding mode insertion algorithm that is going to be different between them since VXRM doesn't need to be save/restored. This also unifies the FRM handling in RISCVISelLowering.cpp between scalar and vector. Fixes outdated comments in RISCVAsmPrinter and sorts the predicate function by the reverse order of the operands being skipped. Reviewed By: eopXD Differential Revision: https://reviews.llvm.org/D158326
128 lines
4.0 KiB
C++
128 lines
4.0 KiB
C++
//===-- RISCVInsertReadWriteCSR.cpp - Insert Read/Write of RISC-V CSR -----===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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// This file implements the machine function pass to insert read/write of CSR-s
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// of the RISC-V instructions.
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//
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// Currently the pass implements:
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// -Naive insertion of a write to vxrm before an RVV fixed-point instruction.
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// -Writing and saving frm before an RVV floating-point instruction with a
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// static rounding mode and restores the value after.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "RISCV.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscv-insert-read-write-csr"
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#define RISCV_INSERT_READ_WRITE_CSR_NAME "RISC-V Insert Read/Write CSR Pass"
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namespace {
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class RISCVInsertReadWriteCSR : public MachineFunctionPass {
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const TargetInstrInfo *TII;
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public:
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static char ID;
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RISCVInsertReadWriteCSR() : MachineFunctionPass(ID) {
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initializeRISCVInsertReadWriteCSRPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return RISCV_INSERT_READ_WRITE_CSR_NAME;
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}
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private:
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bool emitWriteRoundingMode(MachineBasicBlock &MBB);
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};
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} // end anonymous namespace
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char RISCVInsertReadWriteCSR::ID = 0;
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INITIALIZE_PASS(RISCVInsertReadWriteCSR, DEBUG_TYPE,
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RISCV_INSERT_READ_WRITE_CSR_NAME, false, false)
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// This function inserts a write to vxrm when encountering an RVV fixed-point
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// instruction. This function also swaps frm and restores it when encountering
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// an RVV floating point instruction with a static rounding mode.
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bool RISCVInsertReadWriteCSR::emitWriteRoundingMode(MachineBasicBlock &MBB) {
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bool Changed = false;
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for (MachineInstr &MI : MBB) {
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int VXRMIdx = RISCVII::getVXRMOpNum(MI.getDesc());
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if (VXRMIdx >= 0) {
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unsigned VXRMImm = MI.getOperand(VXRMIdx).getImm();
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Changed = true;
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::WriteVXRMImm))
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.addImm(VXRMImm);
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MI.addOperand(MachineOperand::CreateReg(RISCV::VXRM, /*IsDef*/ false,
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/*IsImp*/ true));
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continue;
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}
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int FRMIdx = RISCVII::getFRMOpNum(MI.getDesc());
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if (FRMIdx < 0)
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continue;
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unsigned FRMImm = MI.getOperand(FRMIdx).getImm();
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// The value is a hint to this pass to not alter the frm value.
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if (FRMImm == RISCVFPRndMode::DYN)
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continue;
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Changed = true;
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// Save
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MachineRegisterInfo *MRI = &MBB.getParent()->getRegInfo();
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Register SavedFRM = MRI->createVirtualRegister(&RISCV::GPRRegClass);
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BuildMI(MBB, MI, MI.getDebugLoc(), TII->get(RISCV::SwapFRMImm),
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SavedFRM)
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.addImm(FRMImm);
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MI.addOperand(MachineOperand::CreateReg(RISCV::FRM, /*IsDef*/ false,
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/*IsImp*/ true));
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// Restore
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MachineInstrBuilder MIB =
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BuildMI(*MBB.getParent(), {}, TII->get(RISCV::WriteFRM))
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.addReg(SavedFRM);
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MBB.insertAfter(MI, MIB);
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}
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return Changed;
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}
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bool RISCVInsertReadWriteCSR::runOnMachineFunction(MachineFunction &MF) {
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// Skip if the vector extension is not enabled.
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const RISCVSubtarget &ST = MF.getSubtarget<RISCVSubtarget>();
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if (!ST.hasVInstructions())
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return false;
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TII = ST.getInstrInfo();
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bool Changed = false;
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for (MachineBasicBlock &MBB : MF)
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Changed |= emitWriteRoundingMode(MBB);
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return Changed;
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}
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FunctionPass *llvm::createRISCVInsertReadWriteCSRPass() {
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return new RISCVInsertReadWriteCSR();
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}
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