54cf69c9d5
Summary: This patch introduces a mechanism to check the code object version from the module flag, This avoids checking from command line. In case the module flag is missing, we use the current default code object version supported in the compiler. For tools whose inputs are not IR, we may need other approach (directive, for example) to check the code object version, That will be in a separate patch later. For LIT tests update, we directly add module flag if there is only a single code object version associated with all checks in one file. In cause of multiple code object version in one file, we use the "sed" method to "clone" the checks to achieve the goal. Reviewer: arsenm Differential Revision: https://reviews.llvm.org/D14313
397 lines
13 KiB
LLVM
397 lines
13 KiB
LLVM
; RUN: sed 's/CODE_OBJECT_VERSION/200/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN,HSA %s
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; RUN: sed 's/CODE_OBJECT_VERSION/500/g' %s | llc -mtriple=amdgcn-amd-amdhsa -mcpu=kaveri -verify-machineinstrs | FileCheck -check-prefixes=GCN,COV5 %s
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; RUN: sed 's/CODE_OBJECT_VERSION/400/g' %s | llc -mtriple=amdgcn-mesa-mesa3d -mcpu=tahiti -verify-machineinstrs | FileCheck -check-prefixes=GCN,MESA %s
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 56
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_load_dword s0, s[4:5], 0x0
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; COV5: .amdhsa_kernarg_size 256
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define amdgpu_kernel void @kernel_implicitarg_ptr_empty() #0 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr_empty_0implicit:
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; HSA: enable_sgpr_kernarg_segment_ptr = 0
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; HSA: kernarg_segment_byte_size = 0
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0{{$}}
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; HSA: s_load_dword s0, [[NULL]], 0x0
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; MESA: s_load_dword s0, s[4:5], 0x0
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; COV5: .amdhsa_kernarg_size 0
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define amdgpu_kernel void @kernel_implicitarg_ptr_empty_0implicit() #3 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr_empty:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_load_dword s0, s[4:5], 0x0
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; COV5: .amdhsa_kernarg_size 48
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr_empty() #1 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_ptr:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 168
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 128
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_load_dword s0, s[4:5], 0x1c
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; COV5: .amdhsa_kernarg_size 368
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define amdgpu_kernel void @kernel_implicitarg_ptr([112 x i8]) #0 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_implicitarg_ptr:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 128
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_load_dword s0, s[4:5], 0x1c
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; COV5: .amdhsa_kernarg_size 160
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define amdgpu_kernel void @opencl_kernel_implicitarg_ptr([112 x i8]) #1 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}func_implicitarg_ptr:
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; GCN: s_waitcnt
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; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_implicitarg_ptr:
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; GCN: s_waitcnt
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; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0
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; GCN-NEXT: s_waitcnt
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; GCN-NEXT: s_setpc_b64
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define void @opencl_func_implicitarg_ptr() #0 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 56
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; MESA: kernarg_segment_alignment = 4
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; GCN: s_mov_b64 s[8:9], s[4:5]
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; GCN: s_swappc_b64
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; COV5: .amdhsa_kernarg_size 256
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func_empty_implicit0:
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; HSA: enable_sgpr_kernarg_segment_ptr = 0
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; HSA: kernarg_segment_byte_size = 0
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_mov_b64 s[8:9], 0{{$}}
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; MESA: s_mov_b64 s[8:9], s[4:5]{{$}}
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; GCN: s_swappc_b64
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; COV5: .amdhsa_kernarg_size 0
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func_empty_implicit0() #3 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func_empty:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 48
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 16
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; GCN: s_mov_b64 s[8:9], s[4:5]
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; GCN-NOT: s4
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; GCN-NOT: s5
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; GCN: s_swappc_b64
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; COV5: .amdhsa_kernarg_size 48
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func_empty() #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_implicitarg_ptr_func:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 168
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 128
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; MESA: kernarg_segment_alignment = 4
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; HSA: s_add_u32 s8, s4, 0x70
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; MESA: s_add_u32 s8, s4, 0x70
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; GCN: s_addc_u32 s9, s5, 0{{$}}
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; GCN: s_swappc_b64
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; COV5: .amdhsa_kernarg_size 368
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define amdgpu_kernel void @kernel_call_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_kernel_call_implicitarg_ptr_func:
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; HSA: enable_sgpr_kernarg_segment_ptr = 1
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; HSA: kernarg_segment_byte_size = 160
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; HSA: kernarg_segment_alignment = 4
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; MESA: enable_sgpr_kernarg_segment_ptr = 1
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; MESA: kernarg_segment_byte_size = 128
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; MESA: kernarg_segment_alignment = 4
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; GCN: s_add_u32 s8, s4, 0x70
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; GCN: s_addc_u32 s9, s5, 0{{$}}
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; GCN: s_swappc_b64
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; COV5: .amdhsa_kernarg_size 160
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define amdgpu_kernel void @opencl_kernel_call_implicitarg_ptr_func([112 x i8]) #1 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_call_implicitarg_ptr_func:
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; GCN-NOT: s8
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; GCN-NOT: s9
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; GCN-NOT: s[8:9]
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; GCN: s_swappc_b64
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; GCN: s_setpc_b64 s[30:31]
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define void @func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_call_implicitarg_ptr_func:
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; GCN-NOT: s8
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; GCN-NOT: s9
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; GCN-NOT: s[8:9]
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; GCN: s_swappc_b64
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; GCN: s_setpc_b64 s[30:31]
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define void @opencl_func_call_implicitarg_ptr_func() #0 {
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call void @func_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; GCN-DAG: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0
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; GCN-DAG: s_load_dword s{{[0-9]+}}, [[NULL]], 0x0
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; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0
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; GCN: s_waitcnt lgkmcnt(0)
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define void @func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load0 = load volatile i32, ptr addrspace(4) %kernarg.segment.ptr
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%load1 = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}opencl_func_kernarg_implicitarg_ptr:
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; GCN: s_waitcnt
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; GCN-DAG: s_mov_b64 [[NULL:s\[[0-9]+:[0-9]+\]]], 0
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; GCN-DAG: s_load_dword s{{[0-9]+}}, [[NULL]], 0x0
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; GCN: s_load_dword s{{[0-9]+}}, s[8:9], 0x0
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; GCN: s_waitcnt lgkmcnt(0)
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define void @opencl_func_kernarg_implicitarg_ptr() #0 {
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%kernarg.segment.ptr = call ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr()
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load0 = load volatile i32, ptr addrspace(4) %kernarg.segment.ptr
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%load1 = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; GCN-LABEL: {{^}}kernel_call_kernarg_implicitarg_ptr_func:
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; GCN: s_add_u32 s8, s4, 0x70
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; GCN: s_addc_u32 s9, s5, 0
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; GCN: s_swappc_b64
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define amdgpu_kernel void @kernel_call_kernarg_implicitarg_ptr_func([112 x i8]) #0 {
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call void @func_kernarg_implicitarg_ptr()
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ret void
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}
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; GCN-LABEL: {{^}}kernel_implicitarg_no_struct_align_padding:
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; HSA: kernarg_segment_byte_size = 120
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; HSA: kernarg_segment_alignment = 6
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; MESA: kernarg_segment_byte_size = 84
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; MESA: kernarg_segment_alignment = 6
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; COV5: .amdhsa_kernarg_size 120
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define amdgpu_kernel void @kernel_implicitarg_no_struct_align_padding(<16 x i32>, i32) #1 {
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%implicitarg.ptr = call ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr()
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%load = load volatile i32, ptr addrspace(4) %implicitarg.ptr
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ret void
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}
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; HSA-LABEL: Kernels:
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; HSA-LABEL: - Name: kernel_implicitarg_ptr_empty
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; HSA: CodeProps:
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; HSA: KernargSegmentSize: 56
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_implicitarg_ptr_empty_0implicit
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; HSA: KernargSegmentSize: 0
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; HSA: KernargSegmentAlign: 4
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; HSA-LABEL: - Name: opencl_kernel_implicitarg_ptr_empty
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; HSA: KernargSegmentSize: 48
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_implicitarg_ptr
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; HSA: KernargSegmentSize: 168
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: opencl_kernel_implicitarg_ptr
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; HSA: KernargSegmentSize: 160
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func_empty
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; HSA: KernargSegmentSize: 56
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func_empty_implicit0
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; HSA: KernargSegmentSize: 0
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; HSA: KernargSegmentAlign: 4
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; HSA-LABEL: - Name: opencl_kernel_call_implicitarg_ptr_func_empty
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; HSA: KernargSegmentSize: 48
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_call_implicitarg_ptr_func
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; HSA: KernargSegmentSize: 168
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: opencl_kernel_call_implicitarg_ptr_func
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; HSA: KernargSegmentSize: 160
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_call_kernarg_implicitarg_ptr_func
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; HSA: KernargSegmentSize: 168
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; HSA: KernargSegmentAlign: 8
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; HSA-LABEL: - Name: kernel_implicitarg_no_struct_align_padding
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; HSA: KernargSegmentSize: 120
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; HSA: KernargSegmentAlign: 64
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; COV5-LABEL: amdhsa.kernels:
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 256
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; COV5-LABEL: .name: kernel_implicitarg_ptr_empty
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; COV5: .kernarg_segment_align: 4
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; COV5-NEXT: .kernarg_segment_size: 0
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; COV5-LABEL: .name: kernel_implicitarg_ptr_empty_0implicit
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 48
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; COV5-LABEL: .name: opencl_kernel_implicitarg_ptr_empty
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 368
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; COV5-LABEL: .name: kernel_implicitarg_ptr
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 160
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; COV5-LABEL: .name: opencl_kernel_implicitarg_ptr
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 256
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; COV5-LABEL: .name: kernel_call_implicitarg_ptr_func_empty
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; COV5: .kernarg_segment_align: 4
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; COV5-NEXT: .kernarg_segment_size: 0
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; COV5-LABEL: .name: kernel_call_implicitarg_ptr_func_empty_implicit0
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 48
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; COV5-LABEL: .name: opencl_kernel_call_implicitarg_ptr_func_empty
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 368
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; COV5-LABEL: .name: kernel_call_implicitarg_ptr_func
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 160
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; COV5-LABEL: .name: opencl_kernel_call_implicitarg_ptr_func
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; COV5: .kernarg_segment_align: 8
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; COV5-NEXT: .kernarg_segment_size: 368
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; COV5-LABEL: .name: kernel_call_kernarg_implicitarg_ptr_func
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; COV5: .kernarg_segment_align: 64
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; COV5-NEXT: .kernarg_segment_size: 120
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; COV5-LABEL: .name: kernel_implicitarg_no_struct_align_padding
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declare ptr addrspace(4) @llvm.amdgcn.implicitarg.ptr() #2
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declare ptr addrspace(4) @llvm.amdgcn.kernarg.segment.ptr() #2
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attributes #0 = { nounwind noinline }
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attributes #1 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="48" }
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attributes #2 = { nounwind readnone speculatable }
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attributes #3 = { nounwind noinline "amdgpu-implicitarg-num-bytes"="0" }
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!llvm.module.flags = !{!0}
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!0 = !{i32 1, !"amdgpu_code_object_version", i32 CODE_OBJECT_VERSION}
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