4d42e8b5d1
This reverts commita496c8be6e. The workaround inc26dfc81e2should work around the underlying problem with SUBREG_TO_REG.
127 lines
7.1 KiB
YAML
127 lines
7.1 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast -o - %s | FileCheck -check-prefix=SPILLED %s
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# RUN: llc -march=amdgcn -mcpu=tahiti -run-pass=regallocfast,si-lower-sgpr-spills -o - %s | FileCheck -check-prefix=EXPANDED %s
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# Make sure spill/restore of 352 bit registers works.
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---
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name: spill_restore_sgpr352
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_sgpr352
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; SPILLED-NEXT: SI_SPILL_S352_SAVE killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14, %stack.0, implicit $exec, implicit $sgpr32 :: (store (s352) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14 = SI_SPILL_S352_RESTORE %stack.0, implicit $exec, implicit $sgpr32 :: (load (s352) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; EXPANDED-LABEL: name: spill_restore_sgpr352
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: [[DEF:%[0-9]+]]:vgpr_32 = IMPLICIT_DEF
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; EXPANDED-NEXT: [[V_WRITELANE_B32_:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr4, 0, [[V_WRITELANE_B32_]], implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14, implicit $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr5, 1, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr6, 2, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr7, 3, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr8, 4, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr9, 5, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr10, 6, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr11, 7, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr12, 8, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 $sgpr13, 9, [[V_WRITELANE_B32_1]]
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; EXPANDED-NEXT: [[V_WRITELANE_B32_1:%[0-9]+]]:vgpr_32 = V_WRITELANE_B32 killed $sgpr14, 10, [[V_WRITELANE_B32_1]], implicit killed $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $sgpr4 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 0, implicit-def $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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; EXPANDED-NEXT: $sgpr5 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 1
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; EXPANDED-NEXT: $sgpr6 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 2
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; EXPANDED-NEXT: $sgpr7 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 3
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; EXPANDED-NEXT: $sgpr8 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 4
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; EXPANDED-NEXT: $sgpr9 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 5
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; EXPANDED-NEXT: $sgpr10 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 6
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; EXPANDED-NEXT: $sgpr11 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 7
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; EXPANDED-NEXT: $sgpr12 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 8
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; EXPANDED-NEXT: $sgpr13 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 9
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; EXPANDED-NEXT: $sgpr14 = V_READLANE_B32 [[V_WRITELANE_B32_1]], 10
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $sgpr4_sgpr5_sgpr6_sgpr7_sgpr8_sgpr9_sgpr10_sgpr11_sgpr12_sgpr13_sgpr14
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bb.0:
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S_NOP 0, implicit-def %0:sgpr_352
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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---
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name: spill_restore_vgpr352
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tracksRegLiveness: true
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machineFunctionInfo:
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scratchRSrcReg: $sgpr0_sgpr1_sgpr2_sgpr3
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stackPtrOffsetReg: $sgpr32
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body: |
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; SPILLED-LABEL: name: spill_restore_vgpr352
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; SPILLED: bb.0:
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; SPILLED-NEXT: successors: %bb.1(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
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; SPILLED-NEXT: SI_SPILL_V352_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10, %stack.0, $sgpr32, 0, implicit $exec :: (store (s352) into %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.1:
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; SPILLED-NEXT: successors: %bb.2(0x80000000)
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: S_NOP 1
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; SPILLED-NEXT: {{ $}}
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; SPILLED-NEXT: bb.2:
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; SPILLED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 = SI_SPILL_V352_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s352) from %stack.0, align 4, addrspace 5)
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; SPILLED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
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; EXPANDED-LABEL: name: spill_restore_vgpr352
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; EXPANDED: bb.0:
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; EXPANDED-NEXT: successors: %bb.1(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 0, implicit-def renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
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; EXPANDED-NEXT: SI_SPILL_V352_SAVE killed $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10, %stack.0, $sgpr32, 0, implicit $exec :: (store (s352) into %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_CBRANCH_SCC1 %bb.1, implicit undef $scc
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.1:
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; EXPANDED-NEXT: successors: %bb.2(0x80000000)
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: S_NOP 1
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; EXPANDED-NEXT: {{ $}}
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; EXPANDED-NEXT: bb.2:
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; EXPANDED-NEXT: $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10 = SI_SPILL_V352_RESTORE %stack.0, $sgpr32, 0, implicit $exec :: (load (s352) from %stack.0, align 4, addrspace 5)
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; EXPANDED-NEXT: S_NOP 0, implicit killed renamable $vgpr0_vgpr1_vgpr2_vgpr3_vgpr4_vgpr5_vgpr6_vgpr7_vgpr8_vgpr9_vgpr10
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bb.0:
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S_NOP 0, implicit-def %0:vreg_352
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S_CBRANCH_SCC1 implicit undef $scc, %bb.1
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bb.1:
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S_NOP 1
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bb.2:
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S_NOP 0, implicit %0
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...
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