61ab106f82
D144048 has added preferred function and loop alignment to RISCVSubtarget, but now we need to set them manually for different processors. Tune features that set preferred function/loop align to [2, 64] bytes (align 1 is not here since the min align is 2) are added. These features can be used in processor definitions. Reviewed By: asb Differential Revision: https://reviews.llvm.org/D157832
47 lines
1.4 KiB
LLVM
47 lines
1.4 KiB
LLVM
; RUN: llc < %s -mtriple=riscv64 | FileCheck %s
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; RUN: llc < %s -mtriple=riscv64 -align-loops=16 | FileCheck %s -check-prefix=ALIGN_16
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; RUN: llc < %s -mtriple=riscv64 -align-loops=32 | FileCheck %s -check-prefix=ALIGN_32
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; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-16 | FileCheck %s -check-prefix=ALIGN_16
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; RUN: llc < %s -mtriple=riscv64 -mattr=+pref-loop-align-32 | FileCheck %s -check-prefix=ALIGN_32
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declare void @foo()
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define void @test(i32 %n, i32 %m) nounwind {
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; CHECK-LABEL: test:
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; CHECK-NOT: .p2align
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; CHECK: ret
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; ALIGN_16-LABEL: test:
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; ALIGN_16: .p2align 4{{$}}
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; ALIGN_16-NEXT: .LBB0_1: # %outer
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; ALIGN_16: .p2align 4{{$}}
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; ALIGN_16-NEXT: .LBB0_2: # %inner
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; ALIGN_32-LABEL: test:
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; ALIGN_32: .p2align 5{{$}}
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; ALIGN_32-NEXT: .LBB0_1: # %outer
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; ALIGN_32: .p2align 5{{$}}
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; ALIGN_32-NEXT: .LBB0_2: # %inner
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entry:
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br label %outer
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outer:
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%outer.iv = phi i32 [0, %entry], [%outer.iv.next, %outer_bb]
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br label %inner
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inner:
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%inner.iv = phi i32 [0, %outer], [%inner.iv.next, %inner]
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call void @foo()
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%inner.iv.next = add i32 %inner.iv, 1
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%inner.cond = icmp ne i32 %inner.iv.next, %m
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br i1 %inner.cond, label %inner, label %outer_bb
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outer_bb:
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%outer.iv.next = add i32 %outer.iv, 1
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%outer.cond = icmp ne i32 %outer.iv.next, %n
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br i1 %outer.cond, label %outer, label %exit
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exit:
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ret void
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}
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