49429783b0
Unlike fmaxnum and fminnum, these operations propagate nan and consider -0.0 to be less than +0.0. Without Zfa, we don't have a single instruction for this. The lowering I've used forces the other input to nan if one input is a nan. If both inputs are nan, they get swapped. Then use the fmax or fmin instruction. New ISD nodes are needed because fmaxnum/fminnum to not define the order of -0.0 and +0.0. This lowering ensures the snans are quieted though that is probably not required in default environment). Also ensures non-canonical nans are canonicalized, though I'm also not sure that's needed. Another option could be to use fmax/fmin and then overwrite the result based on the inputs being nan, but I'm not sure we can do that with any less code. Future work will handle nonans FMF, and handling the case where we can prove the input isn't nan. This does fix the crash in #64022, but we need to do more work to avoid scalarization. Reviewed By: fakepaper56 Differential Revision: https://reviews.llvm.org/D156069
165 lines
6.0 KiB
LLVM
165 lines
6.0 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=ilp32d \
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; RUN: | FileCheck -check-prefixes=CHECKIFD,RV32IFD %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+d \
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; RUN: -verify-machineinstrs -target-abi=lp64d \
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; RUN: | FileCheck -check-prefixes=CHECKIFD,RV64IFD %s
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; RUN: sed 's/iXLen/i32/g' %s | llc -mtriple=riscv32 -mattr=+zdinx \
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; RUN: -verify-machineinstrs -target-abi=ilp32 \
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; RUN: | FileCheck -check-prefix=RV32IZFINXZDINX %s
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; RUN: sed 's/iXLen/i64/g' %s | llc -mtriple=riscv64 -mattr=+zdinx \
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; RUN: -verify-machineinstrs -target-abi=lp64 \
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; RUN: | FileCheck -check-prefix=RV64IZFINXZDINX %s
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declare double @llvm.minimum.f64(double, double)
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define double @fminimum_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fminimum_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: feq.d a0, fa0, fa0
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; CHECKIFD-NEXT: fmv.d fa5, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB0_3
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; CHECKIFD-NEXT: # %bb.1:
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB0_4
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; CHECKIFD-NEXT: .LBB0_2:
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; CHECKIFD-NEXT: fmin.d fa0, fa0, fa5
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; CHECKIFD-NEXT: ret
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; CHECKIFD-NEXT: .LBB0_3:
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; CHECKIFD-NEXT: fmv.d fa5, fa0
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: bnez a0, .LBB0_2
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; CHECKIFD-NEXT: .LBB0_4:
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; CHECKIFD-NEXT: fmin.d fa0, fa1, fa5
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fminimum_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
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; RV32IZFINXZDINX-NEXT: mv a4, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_2
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; RV32IZFINXZDINX-NEXT: # %bb.1:
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; RV32IZFINXZDINX-NEXT: mv a4, a0
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; RV32IZFINXZDINX-NEXT: .LBB0_2:
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; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB0_4
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; RV32IZFINXZDINX-NEXT: # %bb.3:
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; RV32IZFINXZDINX-NEXT: mv a0, a2
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; RV32IZFINXZDINX-NEXT: .LBB0_4:
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; RV32IZFINXZDINX-NEXT: fmin.d a0, a0, a4
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: fminimum_f64:
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; RV64IZFINXZDINX: # %bb.0:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
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; RV64IZFINXZDINX-NEXT: mv a2, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_3
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; RV64IZFINXZDINX-NEXT: # %bb.1:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB0_4
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; RV64IZFINXZDINX-NEXT: .LBB0_2:
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; RV64IZFINXZDINX-NEXT: fmin.d a0, a0, a2
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; RV64IZFINXZDINX-NEXT: ret
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; RV64IZFINXZDINX-NEXT: .LBB0_3:
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; RV64IZFINXZDINX-NEXT: mv a2, a0
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: bnez a3, .LBB0_2
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; RV64IZFINXZDINX-NEXT: .LBB0_4:
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; RV64IZFINXZDINX-NEXT: fmin.d a0, a1, a2
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; RV64IZFINXZDINX-NEXT: ret
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%1 = call double @llvm.minimum.f64(double %a, double %b)
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ret double %1
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}
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declare double @llvm.maximum.f64(double, double)
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define double @fmaximum_f64(double %a, double %b) nounwind {
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; CHECKIFD-LABEL: fmaximum_f64:
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; CHECKIFD: # %bb.0:
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; CHECKIFD-NEXT: feq.d a0, fa0, fa0
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; CHECKIFD-NEXT: fmv.d fa5, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB1_3
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; CHECKIFD-NEXT: # %bb.1:
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: beqz a0, .LBB1_4
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; CHECKIFD-NEXT: .LBB1_2:
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; CHECKIFD-NEXT: fmax.d fa0, fa0, fa5
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; CHECKIFD-NEXT: ret
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; CHECKIFD-NEXT: .LBB1_3:
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; CHECKIFD-NEXT: fmv.d fa5, fa0
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; CHECKIFD-NEXT: feq.d a0, fa1, fa1
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; CHECKIFD-NEXT: bnez a0, .LBB1_2
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; CHECKIFD-NEXT: .LBB1_4:
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; CHECKIFD-NEXT: fmax.d fa0, fa1, fa5
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; CHECKIFD-NEXT: ret
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;
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; RV32IZFINXZDINX-LABEL: fmaximum_f64:
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; RV32IZFINXZDINX: # %bb.0:
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; RV32IZFINXZDINX-NEXT: addi sp, sp, -16
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; RV32IZFINXZDINX-NEXT: sw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a2, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a3, 12(sp)
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: feq.d a6, a0, a0
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; RV32IZFINXZDINX-NEXT: mv a4, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_2
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; RV32IZFINXZDINX-NEXT: # %bb.1:
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; RV32IZFINXZDINX-NEXT: mv a4, a0
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; RV32IZFINXZDINX-NEXT: .LBB1_2:
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; RV32IZFINXZDINX-NEXT: feq.d a6, a2, a2
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; RV32IZFINXZDINX-NEXT: bnez a6, .LBB1_4
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; RV32IZFINXZDINX-NEXT: # %bb.3:
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; RV32IZFINXZDINX-NEXT: mv a0, a2
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; RV32IZFINXZDINX-NEXT: .LBB1_4:
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; RV32IZFINXZDINX-NEXT: fmax.d a0, a0, a4
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; RV32IZFINXZDINX-NEXT: sw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: sw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: lw a0, 8(sp)
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; RV32IZFINXZDINX-NEXT: lw a1, 12(sp)
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; RV32IZFINXZDINX-NEXT: addi sp, sp, 16
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; RV32IZFINXZDINX-NEXT: ret
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;
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; RV64IZFINXZDINX-LABEL: fmaximum_f64:
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; RV64IZFINXZDINX: # %bb.0:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a0, a0
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; RV64IZFINXZDINX-NEXT: mv a2, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_3
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; RV64IZFINXZDINX-NEXT: # %bb.1:
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: beqz a3, .LBB1_4
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; RV64IZFINXZDINX-NEXT: .LBB1_2:
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; RV64IZFINXZDINX-NEXT: fmax.d a0, a0, a2
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; RV64IZFINXZDINX-NEXT: ret
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; RV64IZFINXZDINX-NEXT: .LBB1_3:
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; RV64IZFINXZDINX-NEXT: mv a2, a0
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; RV64IZFINXZDINX-NEXT: feq.d a3, a1, a1
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; RV64IZFINXZDINX-NEXT: bnez a3, .LBB1_2
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; RV64IZFINXZDINX-NEXT: .LBB1_4:
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; RV64IZFINXZDINX-NEXT: fmax.d a0, a1, a2
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; RV64IZFINXZDINX-NEXT: ret
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%1 = call double @llvm.maximum.f64(double %a, double %b)
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ret double %1
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}
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;; NOTE: These prefixes are unused and the list is autogenerated. Do not add tests below this line:
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; RV32IFD: {{.*}}
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; RV64IFD: {{.*}}
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