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clang-p2996/llvm/test/CodeGen/RISCV
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Simon Pilgrim 076bee1020 [DAG] getNode() - fold (zext (trunc (assertzext x))) -> (assertzext x) 
If the pre-truncated value was the same width as the extension, and the assertzext guarantees that the extended bits are already zero, then skip the zext/trunc 'zero_extend_inreg' pattern.

Addresses several regressions noticed in D155472
2023-07-31 10:43:11 +01:00
..
GlobalISel
[RISCV][GlobalISel] Test legalization of binary logical instructions with wider types
2023-07-26 15:37:13 -07:00
intrinsics
…
rvv
[DAG] getNode() - fold (zext (trunc (assertzext x))) -> (assertzext x)
2023-07-31 10:43:11 +01:00
add-before-shl.ll
[RISCV] Move Zca/Zcb/Zcd/Zcf/Zcmp/Zcmt out of experimental status.
2023-06-22 09:22:58 -07:00
add-imm.ll
…
addc-adde-sube-subc.ll
…
addcarry.ll
…
addimm-mulimm.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
addrspacecast.ll
…
aext-to-sext.ll
[InstCombine][CGP] Move swapMayExposeCSEOpportunities() fold
2023-06-15 14:17:58 +02:00
align-loops.ll
…
align.ll
[RISCV] RISCVELFTargetObjectFile: use 2-byte alignment for .text if RVC
2023-05-11 13:44:37 -07:00
alloca.ll
…
alu8.ll
…
alu16.ll
…
alu32.ll
…
alu64.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
analyze-branch.ll
…
and-add-lsr.ll
[DAGCombine] Canonicalize operands for visitANDLike
2023-07-24 16:52:04 +08:00
and.ll
…
arith-with-overflow.ll
…
atomic-cmpxchg-branch-on-result.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg-flag.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-cmpxchg.ll
[RISCV] Slightly weaken expanded seq_cst atomic op to match reference mapping in in the spec
2023-03-30 20:47:28 +01:00
atomic-fence.ll
[RISCV] Implement a proposed mapping for Ztso
2023-02-09 12:00:05 -08:00
atomic-load-store.ll
[RISCV] Strengthen atomic ordering for sequentially consistent stores
2023-06-22 15:42:17 +00:00
atomic-rmw.ll
[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
2023-07-25 09:03:45 -07:00
atomic-signext.ll
[RISCV] Add simple DAG combine to pull xor with 1 through select_cc.
2023-07-25 09:03:45 -07:00
atomicrmw-uinc-udec-wrap.ll
[RISCV] Generalize combineAddOfBooleanXor to support any boolean not just setcc.
2023-07-25 09:04:49 -07:00
attributes.ll
[RISCV] Add support for XCVbi extension in CV32E40P
2023-07-28 21:54:10 +08:00
bfloat.ll
Recommit "[RISCV] Implement support for bf16 truncate/extend on hard FP targets"
2023-06-23 17:23:12 -07:00
bitextract-mac.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
bitreverse-shift.ll
…
bittest.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
blockaddress.ll
…
branch_zero.ll
…
branch-on-zero.ll
[RISCV] Enable preferZeroCompareBranch to optimize branch on zero in codegenprepare
2023-02-28 14:43:40 +08:00
branch-relaxation.ll
…
branch.ll
…
bswap-bitreverse.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
bswap-shift.ll
…
byval.ll
…
callee-saved-fpr32s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-fpr64s.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
callee-saved-gprs.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
calling-conv-half.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
calling-conv-ilp32-ilp32f-common.ll
…
calling-conv-ilp32-ilp32f-ilp32d-common.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
calling-conv-ilp32.ll
…
calling-conv-ilp32d.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-ilp32f-ilp32d-common.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-lp64-lp64f-common.ll
…
calling-conv-lp64-lp64f-lp64d-common.ll
…
calling-conv-lp64.ll
…
calling-conv-rv32f-ilp32.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-sext-zext.ll
…
calling-conv-vector-float.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
calling-conv-vector-on-stack.ll
[RISCV] Remove legacy TA/TU pseudo distinction for unary instructions
2023-06-29 07:34:14 -07:00
calls.ll
…
cm_mvas_mvsa.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
cmp-bool.ll
…
codemodel-lowering.ll
[RISCV] Lower extern_weak symbols using the GOT for the medany model
2023-05-31 18:48:21 +01:00
compress-double.ll
[RISCV] Split double out of compress-float.ll. Add Zcf and Zcd RUN lines.
2023-06-27 09:44:51 -07:00
compress-float.ll
[RISCV] Add Zce extension.
2023-07-13 12:22:06 -07:00
compress-inline-asm.ll
…
compress-opt-branch.ll
…
compress-opt-select.ll
…
compress.ll
…
condbinops.ll
[RISCV] A test for conditional binary ops.
2023-07-28 11:08:02 -04:00
condops.ll
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
copy-frameindex.mir
…
copyprop.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
copysign-casts.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
ctlz-cttz-ctpop.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
ctz_zero_return_test.ll
[RISCV] Add DAG combine for CTTZ/CTLZ in the case of input 0
2023-07-19 16:22:04 +02:00
disable-tail-calls.ll
…
disjoint.ll
…
div_minsize.ll
…
div-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
div-pow2.ll
…
div.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
double_reduct.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
double-arith-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-arith.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-br-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-calling-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
double-convert.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-frem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-imm.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics-strict.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-intrinsics.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-isnan.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-maximum-minimum.ll
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
double-mem.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-previous-failure.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv-sat.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-round-conv.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-fcmp.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
double-stack-spill-restore.ll
[RISCV][CodeGen] Support Zdinx on RV32 codegen
2023-05-25 14:13:37 +08:00
double-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
dso_local_equivalent.ll
[MC][CodeGen] Define R_RISCV_PLT32 and lower dso_local_equivalent to it
2023-02-23 01:26:27 +00:00
dwarf-eh.ll
…
early-clobber-tied-def-subreg-liveness.ll
InlineSpiller: Consider copy bundles when looking for snippet copies
2023-06-20 12:26:27 -04:00
eh-dwarf-cfa.ll
…
elf-preemption.ll
…
emutls.ll
[RISCV] Support emulated TLS
2023-03-29 20:55:51 +01:00
exception-pointer-register.ll
…
fastcc-float.ll
…
fastcc-int.ll
…
fastcc-without-f-reg.ll
[RISCV] Use the stack for MVT::f16 for fastcc when there are no other registers available
2023-07-18 19:49:17 -07:00
fixups-diff.ll
[RISCV] Allow delayed decision for ADD/SUB relocations
2023-07-21 08:37:58 -07:00
fli-licm.ll
[CodeGen][ShrinkWrap] Enable PostShrinkWrap by default
2023-05-25 13:56:29 +05:30
float-arith-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-arith.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bit-preserving-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-br-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-frem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-imm.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics-strict.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-intrinsics.ll
[RISCV] Update computeKnownBitsForTargetNode for FPCLASS.
2023-06-29 14:13:01 +08:00
float-isnan.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-maximum-minimum.ll
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
float-mem.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv-sat.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-round-conv.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-fcmp.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
float-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
float-select-verify.ll
[RISCV] Don't use constantpool for floating-point value if the value can be easily constructed by integer sequence and a floating-point move.
2023-02-03 22:42:08 -08:00
float-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
flt-rounds.ll
…
fmax-fmin.ll
…
fold-addi-loadstore.ll
…
fold-binop-into-select.ll
Reapply [RISCV] Fold binary op into select if profitable.
2023-07-14 15:30:54 -04:00
forced-atomics.ll
[RISCV] Strengthen atomic ordering for sequentially consistent stores
2023-06-22 15:42:17 +00:00
fp16-promote.ll
[RISCV] Custom lower FP_TO_FP16 and FP16_TO_FP to correct ABI of of libcall
2023-06-30 16:41:49 +01:00
fp128.ll
…
fp-imm.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
fpclamptosat.ll
[RISCV] Add DAG combine for (fmv_w_x_rv64 (fmv_x_anyextw_rv64 X))
2023-07-05 19:35:13 -07:00
fpenv.ll
…
frame-info.ll
…
frame.ll
[SelectionDAG] Do not second-guess alignment for alloca
2023-02-09 18:45:20 +03:00
frameaddr-returnaddr.ll
…
frm-dependency.ll
…
get-register-invalid.ll
…
get-register-noreserve.ll
…
get-register-reserve.ll
…
get-setcc-result-type.ll
…
ghccc-nest.ll
…
ghccc-rv32.ll
…
ghccc-rv64.ll
…
ghccc-without-f-reg.ll
[RISCV] Support register allocation for GHC when f/d is not specified in the architecture
2023-07-23 22:40:10 -07:00
global-merge-offset.ll
…
global-merge.ll
…
half-arith-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-arith.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-bitmanip-dagcombines.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-br-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-convert-strict.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-convert.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-fcmp-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-frem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-intrinsics.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
half-isnan.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-maximum-minimum.ll
[RISCV] Add lowering for scalar fmaximum/fminimum.
2023-07-24 13:46:35 -07:00
half-mem.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-round-conv-sat.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
half-round-conv.ll
Ignore load/store until stack address computation
2023-06-26 13:50:36 -07:00
half-select-fcmp.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
half-select-icmp.ll
[RISCV] Fold special case (xor (setcc constant, y, setlt), 1) -> (setcc y, constant + 1, setlt)
2023-06-17 10:10:20 +08:00
half-zfa-fli.ll
[RISCV] Pre-commit tests for D145897. NFC
2023-03-14 13:11:11 -07:00
half-zfa.ll
[RISCV] Fix Zfa fceil/ffloor codegen bugs
2023-03-31 12:19:02 -07:00
hoist-global-addr-base.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
hwasan-check-memaccess.ll
…
i32-icmp.ll
…
i64-icmp.ll
…
iabs.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
idiv_large.ll
[CodeGen] Always expand division larger than i128
2023-03-01 15:33:45 +01:00
imm-cse.ll
…
imm.ll
[RISCV] Don't use (ADD (SLLI C, 32), C) to materialize constants when optimizing for size.
2023-06-12 09:52:35 -07:00
indirectbr.ll
…
init-array.ll
…
inline-asm-abi-names.ll
…
inline-asm-clobbers.ll
…
inline-asm-d-abi-names.ll
…
inline-asm-d-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-f-abi-names.ll
…
inline-asm-f-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm-i-constraint-i1.ll
…
inline-asm-invalid.ll
…
inline-asm-S-constraint.ll
…
inline-asm-zfh-constraint-f.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
inline-asm.ll
[RISCV] Don't allow X0 to be used for 'r' constraint in inline assembly
2023-07-10 13:25:17 -07:00
inline-option-directive.ll
[RISCV] Support '.option arch' directive
2023-05-26 18:39:41 +08:00
interrupt-attr-args-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr-callee.ll
…
interrupt-attr-invalid.ll
…
interrupt-attr-nocall.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
interrupt-attr-ret-error.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
interrupt-attr.ll
[RISCV] Simplify the definitions of interrupt CSRs
2023-07-11 11:20:24 +08:00
isel-optnone.ll
…
jumptable.ll
Revert "[CodeGen][ShrinkWrap] Split restore point"
2023-04-13 10:52:28 +05:30
kcfi-isel-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-mir.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
kcfi-patchable-function-prefix.ll
MachineFunction: -fsanitize={function,kcfi}: ensure 4-byte alignment
2023-06-30 09:13:19 -07:00
kcfi.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
lack-of-signed-truncation-check.ll
[RISCV] Fold (select setcc, setcc, setcc) into and/or instructions
2023-05-12 15:06:58 +08:00
large-stack.ll
…
legalize-fneg.ll
…
libcall-tail-calls.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
live-sp.mir
…
llvm.frexp.ll
[RISCV][test] Add RV32I and RV64I RUN lines to llvm.frexp.ll
2023-07-06 13:36:03 +01:00
local-stack-slot-allocation.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
loop-strength-reduce-add-cheaper-than-mul.ll
…
loop-strength-reduce-loop-invar.ll
[RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions
2023-01-24 11:42:37 -08:00
lsr-legaladdimm.ll
…
machine-combiner-mir.ll
…
machine-combiner-strategies.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
machine-combiner.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-combiner.mir
[RISCV] Clear kill flags when forming FMA instructions in MachineCombiner.
2023-07-12 08:03:45 -07:00
machine-cp.mir
…
machine-cse.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
machine-outliner-and-machine-copy-propagation.ll
[RISCV] Fix regression due to interaction of MachineOutliner and MachineCopyPropagation
2023-03-14 17:55:11 +00:00
machine-outliner-cfi.mir
…
machine-outliner-patchable.ll
…
machine-outliner-position.mir
…
machine-outliner-throw.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
machinelicm-address-pseudos.ll
…
machineoutliner-jumptable.mir
…
machineoutliner-pcrel-lo.mir
…
machineoutliner.mir
[MachineOutliner] Add IsOutlined to MachineFunction
2023-04-10 10:57:29 +08:00
MachineSink-implicit-x0.mir
…
macro-fusion-lui-addi.ll
…
make-compressible-for-store-address.mir
…
make-compressible-rv64.mir
…
make-compressible.mir
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mem64.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
mem.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
memcpy-inline.ll
[RISCV] Add memcpy lowering test coverage with and without V
2023-07-24 12:25:09 -07:00
memcpy.ll
[RISCV] Add memcpy lowering test coverage with and without V
2023-07-24 12:25:09 -07:00
memset-inline.ll
[RISCV] Set Fast flag for unaligned memory accesses
2023-07-24 10:58:57 +01:00
min-max.ll
[SelectionDAG] Improve expansion of wide min/max
2023-06-26 10:45:41 -07:00
mir-target-flags.ll
…
miss-sp-restore-eh.ll
…
module-target-abi2.ll
…
module-target-abi3.ll
…
module-target-abi.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
mul.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
musttail-call.ll
…
narrow-shl-cst.ll
…
neg-abs.ll
…
nest-register.ll
…
nomerge.ll
[CodeGen] Fix nomerge attribute not working in tail calls.
2023-05-10 14:25:11 -04:00
nontemporal-scalable.ll
[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain
2023-04-24 20:15:14 -07:00
nontemporal.ll
[RISCV] Support scalar/fix-length vector NTLH intrinsic with different domain
2023-04-24 20:15:14 -07:00
O0-pipeline.ll
[RISCV] Implement KCFI operand bundle lowering
2023-06-23 22:57:56 +00:00
O3-pipeline.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
option-nopic.ll
…
option-norelax.ll
…
option-norvc.ll
…
option-pic.ll
…
option-relax.ll
…
option-rvc.ll
…
optnone-store-no-combine.ll
…
or-is-add.ll
…
out-of-reach-emergency-slot.mir
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
overflow-intrinsic-optimizations.ll
…
overflow-intrinsics.ll
[RISCV] Add special case for i32 uaddo X, -1 on RV64.
2023-04-01 18:54:03 -07:00
patchable-function-entry.ll
[AsmPrinter] Fix placement of function entry comments
2023-04-18 15:01:36 -07:00
pic-models.ll
…
pr40333.ll
…
pr51206.ll
[ShrinkWrap] Use underlying object to rule out stack access.
2023-05-03 09:28:07 +01:00
pr53662.mir
…
pr55201.ll
…
pr56110.ll
…
pr56457.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
pr58025.ll
…
pr58286.ll
…
pr58511.ll
[DAGCombine] Make sure combined nodes are added back to the worklist in topological order.
2023-06-13 09:14:37 +00:00
pr63365.ll
[CodeGenPrepare][RISCV] Remove asserting VH references before erasing the dead GEP
2023-06-18 23:40:47 +08:00
pr63816.ll
[LegalizeDAG] Prevent LegalizeLoadOps from creating extloads that mix int and fp types.
2023-07-12 08:03:35 -07:00
prefetch.ll
[RISCV] Implement prefetch locality by NTLH
2023-07-16 20:32:46 -07:00
push-pop-popret.ll
[RISCV] Add a pass to combine cm.pop and ret insts
2023-07-07 14:04:11 +08:00
readcyclecounter.ll
…
regalloc-last-chance-recoloring-failure.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
rem.ll
…
remat.ll
…
repeated-fp-divisors.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
reserved-reg-errors.ll
…
reserved-regs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
riscv-codegenprepare-asm.ll
…
riscv-codegenprepare.ll
…
rotl-rotr.ll
[DAG] SimplifyDemandedBits - call ComputeKnownBits for constant non-uniform ISD::SRL shift amounts
2023-07-21 14:52:57 +01:00
rv32-fuchsia.ll
[llvm] Prevent building for riscv32-unknown-fuchsia
2023-03-01 19:42:56 +00:00
rv32i-rv64i-float-double.ll
…
rv32i-rv64i-half.ll
…
rv32xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv32xtheadbb.ll
[RISCV] Select signed and unsigned bitfield extracts for XTHeadBb
2023-02-17 21:46:26 +01:00
rv32xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv32zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv32zbb-intrinsic.ll
…
rv32zbb-zbkb.ll
…
rv32zbb.ll
[SelectionDAG] Improve expansion of wide min/max
2023-06-26 10:45:41 -07:00
rv32zbc-intrinsic.ll
…
rv32zbc-zbkc-intrinsic.ll
…
rv32zbkb-intrinsic.ll
…
rv32zbkb.ll
…
rv32zbkx-intrinsic.ll
…
rv32zbs.ll
…
rv32zknd-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknd-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zkne-intrinsic.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv32zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv32zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64-large-stack.ll
…
rv64d-double-convert-strict.ll
…
rv64d-double-convert.ll
…
rv64f-float-convert-strict.ll
…
rv64f-float-convert.ll
[RISCV][CodeGen] Support Zfinx codegen
2023-05-03 00:13:38 +08:00
rv64i-complex-float.ll
…
rv64i-demanded-bits.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64i-double-softfloat.ll
…
rv64i-exhaustive-w-insts.ll
…
rv64i-shift-sext.ll
[RISCV] Use LBU for extloadi8.
2023-03-21 18:52:05 -07:00
rv64i-single-softfloat.ll
…
rv64i-tricky-shifts.ll
…
rv64i-w-insts-legalization.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-exhaustive-w-insts.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
rv64m-w-insts-legalization.ll
…
rv64xtheadba.ll
[RISCV] Add vendor-defined XTHeadBa (address-generation) extension
2023-02-08 07:54:52 +01:00
rv64xtheadbb.ll
[RISCV] Remove unused CHECK prefix from test. NFC
2023-07-30 22:15:54 -07:00
rv64xtheadbs.ll
[RISCV] Add vendor-defined XTHeadBs (single-bit) extension
2023-02-13 16:28:26 +01:00
rv64zba.ll
[RISCV] Optimize multiplication with immediates
2023-04-15 17:29:06 +08:00
rv64zbb-intrinsic.ll
…
rv64zbb-zbkb.ll
…
rv64zbb.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
rv64zbc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbc-zbkc-intrinsic.ll
[RISCV] Improve type promotion for i32 clmulr/clmulh on RV64.
2023-07-18 10:39:25 -07:00
rv64zbkb-intrinsic.ll
[RISCV] Support i32 brev8 intrinsic on RV64.
2023-07-06 17:24:53 -07:00
rv64zbkb.ll
[RISCV] Use PACK in RISCVMatInt for constants that have the same lower and upper 32 bits.
2023-06-06 13:30:33 -07:00
rv64zbkx-intrinsic.ll
…
rv64zbs.ll
…
rv64zfh-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfh-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-convert-strict.ll
[FPEnv][RISCV] Correct strictfp tests.
2023-07-20 10:16:56 -04:00
rv64zfhmin-half-convert.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
rv64zknd-intrinsic.ll
…
rv64zknd-zkne-intrinsic.ll
…
rv64zkne-intrinsic.ll
…
rv64zknh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zknh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade2.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksed-intrinsic-autoupgrade.ll
[RISCV] Change the immediate argument to Zk* intrinsics/builtins from i8 to i32.
2023-06-13 10:39:43 -07:00
rv64zksed-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic-autoupgrade.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rv64zksh-intrinsic.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
rve.ll
[RISCV][MC] Add support for RV64E
2023-03-23 12:32:25 +00:00
sadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
sadd_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
saverestore-scs.ll
[CodeGen][RISCV] Change Shadow Call Stack Register to X3
2023-04-12 21:06:22 +00:00
saverestore.ll
[RISCV] Update some tests that used "interrupt"="user". NFC
2023-05-31 20:31:24 -07:00
sdata-limit-0.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-4.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-limit-8.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
sdata-local-sym.ll
[RISCV] Allow mismatched SmallDataLimit and use Min for conflicting values
2023-02-07 17:13:21 -08:00
select-and.ll
…
select-bare.ll
…
select-binop-identity.ll
[RISCV] Add codegen for the experimental zicond extension
2023-03-30 21:05:22 +01:00
select-cc.ll
…
select-const.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-constant-xor.ll
…
select-optimize-multiple.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
select-optimize-multiple.mir
…
select-or.ll
…
select.ll
[RISCV] Use RISCVISD::CZERO_EQZ/CZERO_NEZ for XVentanaCondOps.
2023-07-18 10:18:02 -07:00
selectcc-to-shiftand.ll
…
setcc-logic.ll
…
sext-zext-trunc.ll
[LegalizeTypes][RISCV] Add a special case for (add X, -1) to ExpandIntRes_ADDSUB
2023-03-24 09:45:43 +08:00
sextw-removal.ll
[RISCV] Re-define sha256, Zksed, and Zksh intrinsics to use i32 types.
2023-07-17 08:58:29 -07:00
shadowcallstack.ll
[RISCV] Make SCS prologue interrupt safe on RISC-V
2023-04-26 15:58:09 +00:00
shift-amount-mod.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shift-and.ll
…
shift-masked-shamt.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shifts.ll
[RISCV] Add DAG combine to fold (sub 0, (setcc x, 0, setlt)) -> (sra x , xlen - 1)
2023-04-07 08:59:28 +08:00
shl-demanded.ll
…
shlimm-addimm.ll
…
short-foward-branch-opt.ll
…
shrinkwrap-jump-table.ll
[ShrinkWrap] Allow shrinkwrapping past memory accesses to jump tables
2023-05-11 11:33:18 -07:00
shrinkwrap.ll
…
signbit-test.ll
…
signed-truncation-check.ll
[RISCV] Enable signed truncation check transforms for i8
2023-05-10 22:53:24 +08:00
sink-icmp.ll
…
spill-fpr-scalar.ll
[RISCV] Upgrade Zvfh version to 1.0 and move out of experimental state.
2023-07-19 10:03:57 -07:00
split-offsets.ll
[RISCV] Pre-commit test case from PR62734. NFC
2023-05-16 16:07:23 -07:00
split-sp-adjust.ll
…
split-store.ll
[RISCV] Implement isMultiStoresCheaperThanBitsMerge hook
2023-01-31 12:47:48 +00:00
split-udiv-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
split-urem-by-constant.ll
Revert "Revert "[RISCV] Add special case to selectImm for constants that can be created with (ADD (SLLI C, 32), C).""
2023-06-06 17:39:05 -07:00
srem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
srem-seteq-illegal-types.ll
[RISCV] Remove legacy TA/TU pseudo distinction for binary instructions
2023-07-11 10:21:42 -07:00
srem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
ssub_sat.ll
[RISCV] Enable machine copy propagation for copy-like instructions
2023-03-07 17:54:05 +08:00
stack-folding.ll
…
stack-protector-target.ll
[RISCV] Clean up stack-protector-target test
2023-02-06 16:42:59 -08:00
stack-realignment-with-variable-sized-objects.ll
…
stack-realignment.ll
…
stack-slot-coloring.mir
[RISCV] Set how many bytes load from or store to stack slot
2023-03-10 10:14:59 +08:00
stack-slot-size.ll
…
stack-store-check.ll
…
subtarget-features-std-ext.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
switch-width.ll
…
tagged-globals.ll
…
tail-calls.ll
[RISCV] Permit tail call to an externally-defined function with weak linkage
2023-02-03 09:38:46 +08:00
target-abi-invalid.ll
…
target-abi-valid.ll
…
thread-pointer.ll
…
tls-models.ll
…
trunc-free.ll
…
uadd_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
uadd_sat.ll
…
umulo-128-legalisation-lowering.ll
…
unaligned-load-store.ll
[RISCV] Set Fast flag for unaligned memory accesses
2023-07-24 10:58:57 +01:00
unfold-masked-merge-scalar-variablemask.ll
…
unroll-loop-cse.ll
…
urem-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
urem-seteq-illegal-types.ll
Reapply "[RISCV][InsertVSETVLI] Avoid VL toggles for extractelement patterns"
2023-05-10 11:51:51 -07:00
urem-vector-lkk.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat_plus.ll
[RISCV] Add MULW to RISCVStripWSuffix.
2023-03-16 19:42:33 -07:00
usub_sat.ll
…
vararg.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
vector-abi.ll
…
verify-instr.mir
…
vlenb.ll
…
vscale-demanded-bits.ll
SelectionDAG: Teach ComputeKnownBits about VSCALE
2023-05-26 10:48:49 -07:00
wide-mem.ll
…
wide-scalar-shift-by-byte-multiple-legalization.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
wide-scalar-shift-legalization.ll
[RISCV] Remove unused check prefixes for tests. NFC
2023-07-24 13:42:49 +08:00
xaluo.ll
[RISCV] Handle seteq/setne conditions for CZERO_NEZ/CZERO_EQZ during isel.
2023-07-26 10:06:08 -07:00
xtheadfmemidx.ll
[RISCV] Move compressible registers to the beginning of the FP allocation order.
2023-03-27 17:29:28 -07:00
xtheadmac.ll
[RISCV] xtheadmac: fix commutativity issue for the in/out register
2023-02-17 19:45:22 +01:00
xtheadmemidx.ll
[RISCV] Add vendor-defined XTheadMemIdx (Indexed Memory Operations) extension
2023-02-24 00:17:58 +01:00
xtheadmempair.ll
[RISCV] XTHeadMemPair: Fix invalid mempair combine for types other than i32/i64
2023-02-22 19:57:37 +01:00
zbb-cmp-combine.ll
[DAGCombiner] Change foldAndOrOfSETCC() to optimize and/or patterns
2023-07-17 17:13:47 -07:00
zdinx-boundary-check.ll
[RISCV] Add more tests in zdinx-boundary-check.ll
2023-05-30 14:49:33 +08:00
zext-with-load-is-free.ll
…
zfbfmin.ll
[RISCV] Add codegen for Zfbfmin instructions
2023-07-24 10:37:58 +08:00
zfh-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfh-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics-strict.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-half-intrinsics.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zfhmin-imm.ll
[RISCV][CodeGen] Support Zhinx and Zhinxmin
2023-05-12 18:31:35 +10:00
zmmul.ll
…