eae26b6640
Instcombine prefers this canonical form (see getPreferredVectorIndex), as does IRBuilder when passing the index as an integer so we may as well use the prefered form from creation. NOTE: All test changes are mechanical with nothing else expected beyond a change of index type from i32 to i64. Differential Revision: https://reviews.llvm.org/D140983
221 lines
9.5 KiB
LLVM
221 lines
9.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=loop-vectorize -force-vector-width=4 -S | FileCheck %s
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; The function finds the smallest value from a float vector.
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; Check if vectorization is enabled by instruction flag `fcmp nnan`.
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define float @minloop(ptr nocapture readonly %arg) {
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; CHECK-LABEL: @minloop(
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; CHECK-NEXT: top:
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; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
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; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
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; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]
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; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4
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; CHECK-NEXT: [[T5:%.*]] = fcmp nnan olt float [[T2]], [[T4]]
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; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
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; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
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; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
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; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]
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; CHECK: out:
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; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[T6_LCSSA]]
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;
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top:
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%t = load float, ptr %arg
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br label %loop
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loop: ; preds = %loop, %top
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%t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
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%t2 = phi float [ %t6, %loop ], [ %t, %top ]
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%t3 = getelementptr float, ptr %arg, i64 %t1
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%t4 = load float, ptr %t3, align 4
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%t5 = fcmp nnan olt float %t2, %t4
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%t6 = select i1 %t5, float %t2, float %t4
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%t7 = add i64 %t1, 1
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%t8 = icmp eq i64 %t7, 65537
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br i1 %t8, label %out, label %loop
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out: ; preds = %loop
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ret float %t6
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}
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; Check if vectorization is still enabled by function attribute.
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define float @minloopattr(ptr nocapture readonly %arg) #0 {
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; CHECK-LABEL: @minloopattr(
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; CHECK-NEXT: top:
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; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 4
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; CHECK-NEXT: br i1 false, label [[SCALAR_PH:%.*]], label [[VECTOR_PH:%.*]]
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; CHECK: vector.ph:
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; CHECK-NEXT: [[MINMAX_IDENT_SPLATINSERT:%.*]] = insertelement <4 x float> poison, float [[T]], i64 0
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; CHECK-NEXT: [[MINMAX_IDENT_SPLAT:%.*]] = shufflevector <4 x float> [[MINMAX_IDENT_SPLATINSERT]], <4 x float> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: br label [[VECTOR_BODY:%.*]]
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; CHECK: vector.body:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i64 [ 0, [[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[VEC_PHI:%.*]] = phi <4 x float> [ [[MINMAX_IDENT_SPLAT]], [[VECTOR_PH]] ], [ [[TMP4:%.*]], [[VECTOR_BODY]] ]
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; CHECK-NEXT: [[OFFSET_IDX:%.*]] = add i64 1, [[INDEX]]
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; CHECK-NEXT: [[TMP0:%.*]] = add i64 [[OFFSET_IDX]], 0
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; CHECK-NEXT: [[TMP1:%.*]] = getelementptr float, ptr [[ARG]], i64 [[TMP0]]
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; CHECK-NEXT: [[TMP2:%.*]] = getelementptr float, ptr [[TMP1]], i32 0
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x float>, ptr [[TMP2]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = fcmp olt <4 x float> [[VEC_PHI]], [[WIDE_LOAD]]
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; CHECK-NEXT: [[TMP4]] = select <4 x i1> [[TMP3]], <4 x float> [[VEC_PHI]], <4 x float> [[WIDE_LOAD]]
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i64 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i64 [[INDEX_NEXT]], 65536
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; CHECK-NEXT: br i1 [[TMP5]], label [[MIDDLE_BLOCK:%.*]], label [[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: middle.block:
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; CHECK-NEXT: [[TMP6:%.*]] = call float @llvm.vector.reduce.fmin.v4f32(<4 x float> [[TMP4]])
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; CHECK-NEXT: [[CMP_N:%.*]] = icmp eq i64 65536, 65536
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; CHECK-NEXT: br i1 [[CMP_N]], label [[OUT:%.*]], label [[SCALAR_PH]]
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; CHECK: scalar.ph:
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; CHECK-NEXT: [[BC_RESUME_VAL:%.*]] = phi i64 [ 65537, [[MIDDLE_BLOCK]] ], [ 1, [[TOP:%.*]] ]
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; CHECK-NEXT: [[BC_MERGE_RDX:%.*]] = phi float [ [[T]], [[TOP]] ], [ [[TMP6]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ [[BC_RESUME_VAL]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[BC_MERGE_RDX]], [[SCALAR_PH]] ]
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; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]
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; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4
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; CHECK-NEXT: [[T5:%.*]] = fcmp olt float [[T2]], [[T4]]
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; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
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; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
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; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
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; CHECK-NEXT: br i1 [[T8]], label [[OUT]], label [[LOOP]], !llvm.loop [[LOOP2:![0-9]+]]
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; CHECK: out:
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; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ], [ [[TMP6]], [[MIDDLE_BLOCK]] ]
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; CHECK-NEXT: ret float [[T6_LCSSA]]
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;
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top:
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%t = load float, ptr %arg
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br label %loop
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loop: ; preds = %loop, %top
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%t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
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%t2 = phi float [ %t6, %loop ], [ %t, %top ]
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%t3 = getelementptr float, ptr %arg, i64 %t1
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%t4 = load float, ptr %t3, align 4
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%t5 = fcmp olt float %t2, %t4
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%t6 = select i1 %t5, float %t2, float %t4
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%t7 = add i64 %t1, 1
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%t8 = icmp eq i64 %t7, 65537
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br i1 %t8, label %out, label %loop
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out: ; preds = %loop
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ret float %t6
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}
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; Check if vectorization is prevented without the flag or attribute.
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define float @minloopnovec(ptr nocapture readonly %arg) {
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; CHECK-LABEL: @minloopnovec(
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; CHECK-NEXT: top:
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; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
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; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
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; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]
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; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4
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; CHECK-NEXT: [[T5:%.*]] = fcmp olt float [[T2]], [[T4]]
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; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
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; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
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; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
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; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]
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; CHECK: out:
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; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[T6_LCSSA]]
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;
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top:
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%t = load float, ptr %arg
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br label %loop
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loop: ; preds = %loop, %top
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%t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
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%t2 = phi float [ %t6, %loop ], [ %t, %top ]
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%t3 = getelementptr float, ptr %arg, i64 %t1
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%t4 = load float, ptr %t3, align 4
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%t5 = fcmp olt float %t2, %t4
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%t6 = select i1 %t5, float %t2, float %t4
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%t7 = add i64 %t1, 1
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%t8 = icmp eq i64 %t7, 65537
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br i1 %t8, label %out, label %loop
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out: ; preds = %loop
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ret float %t6
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}
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; This test is checking that we don't vectorize when only one of the required attributes is set.
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; Note that this test should not vectorize even after switching to IR-level FMF.
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define float @minloopmissingnsz(ptr nocapture readonly %arg) #1 {
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; CHECK-LABEL: @minloopmissingnsz(
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; CHECK-NEXT: top:
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; CHECK-NEXT: [[T:%.*]] = load float, ptr [[ARG:%.*]], align 4
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[T1:%.*]] = phi i64 [ [[T7:%.*]], [[LOOP]] ], [ 1, [[TOP:%.*]] ]
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; CHECK-NEXT: [[T2:%.*]] = phi float [ [[T6:%.*]], [[LOOP]] ], [ [[T]], [[TOP]] ]
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; CHECK-NEXT: [[T3:%.*]] = getelementptr float, ptr [[ARG]], i64 [[T1]]
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; CHECK-NEXT: [[T4:%.*]] = load float, ptr [[T3]], align 4
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; CHECK-NEXT: [[T5:%.*]] = fcmp olt float [[T2]], [[T4]]
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; CHECK-NEXT: [[T6]] = select i1 [[T5]], float [[T2]], float [[T4]]
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; CHECK-NEXT: [[T7]] = add i64 [[T1]], 1
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; CHECK-NEXT: [[T8:%.*]] = icmp eq i64 [[T7]], 65537
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; CHECK-NEXT: br i1 [[T8]], label [[OUT:%.*]], label [[LOOP]]
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; CHECK: out:
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; CHECK-NEXT: [[T6_LCSSA:%.*]] = phi float [ [[T6]], [[LOOP]] ]
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; CHECK-NEXT: ret float [[T6_LCSSA]]
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;
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top:
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%t = load float, ptr %arg
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br label %loop
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loop: ; preds = %loop, %top
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%t1 = phi i64 [ %t7, %loop ], [ 1, %top ]
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%t2 = phi float [ %t6, %loop ], [ %t, %top ]
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%t3 = getelementptr float, ptr %arg, i64 %t1
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%t4 = load float, ptr %t3, align 4
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%t5 = fcmp olt float %t2, %t4
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%t6 = select i1 %t5, float %t2, float %t4
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%t7 = add i64 %t1, 1
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%t8 = icmp eq i64 %t7, 65537
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br i1 %t8, label %out, label %loop
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out: ; preds = %loop
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ret float %t6
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}
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; This would assert on FMF propagation.
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define void @not_a_min_max() {
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; CHECK-LABEL: @not_a_min_max(
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; CHECK-NEXT: entry:
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; CHECK-NEXT: br label [[LOOP:%.*]]
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; CHECK: loop:
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; CHECK-NEXT: [[F9_S0_V0:%.*]] = phi i32 [ 0, [[ENTRY:%.*]] ], [ [[ADD:%.*]], [[LOOP]] ]
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; CHECK-NEXT: [[T14:%.*]] = icmp eq i32 [[F9_S0_V0]], 5
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; CHECK-NEXT: [[T15:%.*]] = select reassoc nnan ninf nsz contract afn i1 [[T14]], float 0x36A0000000000000, float 0.000000e+00
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; CHECK-NEXT: [[ADD]] = add nuw nsw i32 [[F9_S0_V0]], 1
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; CHECK-NEXT: br i1 false, label [[END:%.*]], label [[LOOP]]
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; CHECK: end:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%f9.s0.v0 = phi i32 [ 0, %entry ], [ %add, %loop ]
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%t14 = icmp eq i32 %f9.s0.v0, 5
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%t15 = select reassoc nnan ninf nsz contract afn i1 %t14, float 0x36A0000000000000, float 0.0
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%add = add nuw nsw i32 %f9.s0.v0, 1
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br i1 false, label %end, label %loop
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end:
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ret void
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}
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attributes #0 = { "no-nans-fp-math"="true" "no-signed-zeros-fp-math"="true" }
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attributes #1 = { "no-nans-fp-math"="true" }
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