Tony Tye c62b737ad6 [AMDGPU] Correct rmw atomics s_waitcnt generation ...

The AMD GPU SIMemoryLegalizer was using the ordering address space
rather than the instruction address space when determining the
s_waitcnt to generate to ensure that a read-modify-write atomic has
completed. This resulted in additional unnecessary counters being
waited on.

Differential Revision: https://reviews.llvm.org/D96743

2021-02-17 01:32:29 +00:00

3.3 KiB

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