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clang-p2996/llvm/lib/Target/RISCV
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Michael Maitland 3967510032 [RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (#79343) 
…ctor CC.
2024-01-24 16:03:38 -05:00
..
AsmParser
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
Disassembler
[RISCV] Re-implement Zacas MC layer support to make it usable for CodeGen. (#77418)
2024-01-10 09:18:40 -08:00
GISel
[RISCV][GISel] First mask argument placed in v0 according to RISCV Ve… (#79343)
2024-01-24 16:03:38 -05:00
MCA
[RISCV][llvm-mca] Use correct LMUL and SEW for strided loads and stores (#76869)
2024-01-04 15:40:30 -05:00
MCTargetDesc
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
TargetInfo
…
CMakeLists.txt
[RISCV] Add missing component Scalar (#71905)
2023-11-10 16:43:42 +08:00
RISCV.h
[Target] Remove unused forward declarations (NFC)
2023-12-10 10:38:55 -08:00
RISCV.td
[RISCV] Add scheduler model for sifive-p450. (#77989)
2024-01-16 08:43:09 -08:00
RISCVAsmPrinter.cpp
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
RISCVCallingConv.td
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
RISCVCodeGenPrepare.cpp
[RISCV] Don't look for sext in RISCVCodeGenPrepare::visitAnd.
2024-01-19 14:44:47 -08:00
RISCVCombine.td
[RISCV][GISel] Add a post legalizer combiner and enable a couple comb… (#67053)
2023-09-22 10:13:56 -07:00
RISCVDeadRegisterDefinitions.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVExpandAtomicPseudoInsts.cpp
[RISCV] Prevent tryToFoldBNEOnCmpXchgResult from deleting AND if it has others users.
2023-08-28 10:11:12 -07:00
RISCVExpandPseudoInsts.cpp
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
RISCVFeatures.td
[RISCV] Move FeatureStdExtH in RISCVFeatures.td. NFC
2024-01-23 12:18:14 -08:00
RISCVFoldMasks.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVFrameLowering.cpp
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
RISCVFrameLowering.h
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
RISCVGatherScatterLowering.cpp
[RISCV] Don't check haveNoCommonBitsSet in RISCVGatherScatterLowering
2024-01-15 14:09:52 +07:00
RISCVGISel.td
[RISCV][GISel] Support G_ROTL/G_ROTR with Zbb. (#72825)
2023-12-04 13:00:34 -08:00
RISCVInsertReadWriteCSR.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVInsertVSETVLI.cpp
[RISCV] Add statistic support for VSETVL insertion pass (#78543)
2024-01-19 08:22:25 +08:00
RISCVInsertWriteVXRM.cpp
[RISCV] Don't emit vxrm writes for vnclip(u).wi with shift of 0. (#76578)
2024-01-02 09:50:06 -08:00
RISCVInstrFormats.td
[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)
2023-12-27 11:19:38 +08:00
RISCVInstrFormatsC.td
…
RISCVInstrFormatsV.td
…
RISCVInstrGISel.td
[RISCV][GISel] Add support for G_IS_FPCLASS in F and D extensions (#72000)
2023-11-22 16:43:20 -08:00
RISCVInstrInfo.cpp
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
RISCVInstrInfo.h
Revert "[RISCV] Implement RISCVInsrInfo::getConstValDefinedInReg"
2024-01-17 19:27:36 +00:00
RISCVInstrInfo.td
[RISCV] Support TLSDESC in the RISC-V backend (#66915)
2024-01-23 16:16:07 -08:00
RISCVInstrInfoA.td
[RISCV] Support isel for Zacas for XLen and i32. (#77666)
2024-01-10 12:00:40 -08:00
RISCVInstrInfoC.td
[RISCV] Add CompressPat for c.beqz/bnez with X0 in the first operand. (#69042)
2023-10-14 08:12:46 -07:00
RISCVInstrInfoD.td
[RISCV] Refactor GPRF64 register class to make it usable for Zacas. (#77408)
2024-01-09 09:21:27 -08:00
RISCVInstrInfoF.td
[RISCV][NFC] Rename RISCVISD::FPCLASS to RISCVISD::FCLASS
2023-11-22 16:24:05 -08:00
RISCVInstrInfoM.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoV.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoVPseudos.td
[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)
2024-01-16 13:36:24 +07:00
RISCVInstrInfoVSDPatterns.td
[RISCV][ISel] Use vaaddu with rounding mode rnu for ISD::AVGCEILU. (#77473)
2024-01-10 12:08:16 +09:00
RISCVInstrInfoVVLPatterns.td
[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)
2024-01-16 13:36:24 +07:00
RISCVInstrInfoXCV.td
[RISCV] Implement intrinsics for XCVbitmanip extension in CV32E40P (#74993)
2023-12-17 19:29:40 +08:00
RISCVInstrInfoXSf.td
[RISCV] Allow VCIX with SE to reorder (#77049)
2024-01-24 11:30:12 +08:00
RISCVInstrInfoXTHead.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoXVentana.td
[RISCV] Rename Ventana DecoderNamespace to XVentana for matching other extension. NFC.
2023-08-19 12:44:59 +08:00
RISCVInstrInfoZa.td
[RISCV] Support isel for Zacas for XLen and i32. (#77666)
2024-01-10 12:00:40 -08:00
RISCVInstrInfoZb.td
[RISCV] Add more Zbs patterns for -riscv-experimental-rv64-legal-i32.
2023-11-21 23:24:00 -08:00
RISCVInstrInfoZc.td
[RISCV] Update DecoderMethod and MCOperandPredicate of spimm. (#76061)
2023-12-27 09:11:34 +08:00
RISCVInstrInfoZcmop.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZfa.td
[RISCV] Apply IsSignExtendingOpW = 1 on fcvtmod.w.d (#69633)
2023-10-19 14:55:33 -07:00
RISCVInstrInfoZfbfmin.td
[RISCV] Add experimental support for making i32 a legal type on RV64 in SelectionDAG. (#70357)
2023-11-01 09:36:41 -07:00
RISCVInstrInfoZfh.td
[RISCV] Combine HasStdExtZfhOrZfhmin and HasStdExtZfhmin. NFC (#78826)
2024-01-22 13:06:37 -08:00
RISCVInstrInfoZicbo.td
[RISCV] Match prefetch address with offset (#66072)
2023-10-20 14:22:48 +08:00
RISCVInstrInfoZicfiss.td
[RISCV] Add MC layer support for Zicfiss. (#66043)
2023-12-30 15:40:20 +08:00
RISCVInstrInfoZicond.td
…
RISCVInstrInfoZimop.td
[RISCV] Move Zimop to RISCVInstrInfoZimop.td (#76392)
2023-12-27 11:19:38 +08:00
RISCVInstrInfoZk.td
[RISCV][NFC] Add base classes of Operand and uimm/simm (#68472)
2023-10-08 14:13:08 +08:00
RISCVInstrInfoZvfbf.td
…
RISCVInstrInfoZvk.td
[RISCV] Remove experimental from Vector Crypto extensions (#74213)
2023-12-18 22:04:22 -08:00
RISCVISelDAGToDAG.cpp
[RISCV] Update performCombineVMergeAndVOps comments. NFC (#78472)
2024-01-24 12:53:33 +07:00
RISCVISelDAGToDAG.h
[RISCV] Disable performCombineVMergeAndVOps for PseduoVIOTA_M. (#71483)
2023-11-07 16:21:35 +08:00
RISCVISelLowering.cpp
[RISCV] Separate single source and dual source lowering code [nfc]
2024-01-24 09:16:50 -08:00
RISCVISelLowering.h
[RISCV] Allow VCIX with SE to reorder (#77049)
2024-01-24 11:30:12 +08:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
[RISCV] Fix wrong offset use caused by missing the size of Zcmp push. (#66613)
2023-09-25 12:05:05 +08:00
RISCVMacroFusion.cpp
[RISCV] Split TuneShiftedZExtFusion (#76032)
2023-12-22 14:37:26 +08:00
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVMergeBaseOffset.cpp
[RISCV] Merge ADDI with X0 into base offset (#78940)
2024-01-23 09:57:05 +08:00
RISCVMoveMerger.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVOptWInstrs.cpp
[RISCV] Remove vmv.s.x and vmv.x.s lmul pseudo variants (#71501)
2024-01-16 13:36:24 +07:00
RISCVPostRAExpandPseudoInsts.cpp
[RISCV][NFC] Pass MCSubtargetInfo instead of FeatureBitset in RISCVMatInt (#71770)
2023-11-09 15:15:23 +08:00
RISCVProcessors.td
[RISCV] Add sifive-p670 processor (#79015)
2024-01-23 21:45:24 -05:00
RISCVPushPopOptimizer.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Allow VCIX with SE to reorder (#77049)
2024-01-24 11:30:12 +08:00
RISCVRegisterInfo.h
…
RISCVRegisterInfo.td
[RISCV] Allow VCIX with SE to reorder (#77049)
2024-01-24 11:30:12 +08:00
RISCVRVVInitUndef.cpp
[RISCV] Cleanup pass initialization.
2023-12-07 18:21:38 -08:00
RISCVSchedRocket.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedSiFive7.td
[RISCV][MISched] Set EnableIntervals to true for SiFive7 (#75681)
2023-12-19 11:03:03 -05:00
RISCVSchedSiFiveP400.td
[RISCV] Add scheduler model for sifive-p450. (#77989)
2024-01-16 08:43:09 -08:00
RISCVSchedSyntacoreSCR1.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVSchedule.td
[RISCV] Separate addend from FMA operands to support cascade FMA. NFC. (#70241)
2023-10-26 13:00:36 +08:00
RISCVScheduleV.td
[RISCV] Remove SiFive7PipeV and replace it with SiFive7VCQ (#73969)
2023-12-04 17:21:02 -05:00
RISCVScheduleZb.td
…
RISCVSubtarget.cpp
[RISCV] Add MinimumJumpTableEntries to TuneInfo (#72963)
2023-11-23 14:05:23 +08:00
RISCVSubtarget.h
[RISCV] Add branch+c.mv macrofusion for sifive-p450. (#76169)
2024-01-08 15:23:26 -08:00
RISCVSystemOperands.td
[RISCV] Remove XSfcie extension.
2023-12-28 13:54:15 -08:00
RISCVTargetMachine.cpp
[RISCV] CodeGen of RVE and ilp32e/lp64e ABIs (#76777)
2024-01-16 20:44:30 +08:00
RISCVTargetMachine.h
[NFC][CodeGen] Change CodeGenOpt::Level/CodeGenFileType into enum classes (#66295)
2023-09-14 14:10:14 -07:00
RISCVTargetObjectFile.cpp
[llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003)
2024-01-16 15:32:35 -08:00
RISCVTargetObjectFile.h
[llvm] Indirect symbol replacement with GOTPCREL for aarch64 and risc… (#78003)
2024-01-16 15:32:35 -08:00
RISCVTargetTransformInfo.cpp
[RISCV][CostModel] Make VMV_S_X and VMV_X_S cost independent of LMUL (#78739)
2024-01-23 11:00:19 +08:00
RISCVTargetTransformInfo.h
Revert "[LSR][TTI][RISCV] Disable terminator folding for RISC-V."
2024-01-11 13:20:02 -08:00