9e9907f1cf
Similar to 806761a762.
For IR files without a target triple, -mtriple= specifies the full
target triple while -march= merely sets the architecture part of the
default target triple, leaving a target triple which may not make sense,
e.g. amdgpu-apple-darwin.
Therefore, -march= is error-prone and not recommended for tests without
a target triple. The issue has been benign as we recognize
$unknown-apple-darwin as ELF instead of rejecting it outrightly.
This patch changes AMDGPU tests to not rely on the default
OS/environment components. Tests that need fixes are not changed:
```
LLVM :: CodeGen/AMDGPU/fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fabs.ll
LLVM :: CodeGen/AMDGPU/floor.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.f64.ll
LLVM :: CodeGen/AMDGPU/fneg-fabs.ll
LLVM :: CodeGen/AMDGPU/r600-infinite-loop-bug-while-reorganizing-vector.ll
LLVM :: CodeGen/AMDGPU/schedule-if-2.ll
```
45 lines
1.2 KiB
LLVM
45 lines
1.2 KiB
LLVM
; RUN: llc -O0 -mtriple=amdgcn -verify-machineinstrs < %s | FileCheck %s
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; Test that the alignment of kernel arguments does not impact the
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; alignment of the stack
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; CHECK-LABEL: {{^}}no_args:
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; CHECK: ScratchSize: 5{{$}}
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define amdgpu_kernel void @no_args() {
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%alloca = alloca i8, addrspace(5)
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store volatile i8 0, ptr addrspace(5) %alloca
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ret void
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}
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; CHECK-LABEL: {{^}}force_align32:
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; CHECK: ScratchSize: 5{{$}}
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define amdgpu_kernel void @force_align32(<8 x i32>) {
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%alloca = alloca i8, addrspace(5)
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store volatile i8 0, ptr addrspace(5) %alloca
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ret void
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}
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; CHECK-LABEL: {{^}}force_align64:
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; CHECK: ScratchSize: 5{{$}}
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define amdgpu_kernel void @force_align64(<16 x i32>) {
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%alloca = alloca i8, addrspace(5)
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store volatile i8 0, ptr addrspace(5) %alloca
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ret void
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}
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; CHECK-LABEL: {{^}}force_align128:
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; CHECK: ScratchSize: 5{{$}}
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define amdgpu_kernel void @force_align128(<32 x i32>) {
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%alloca = alloca i8, addrspace(5)
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store volatile i8 0, ptr addrspace(5) %alloca
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ret void
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}
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; CHECK-LABEL: {{^}}force_align256:
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; CHECK: ScratchSize: 5{{$}}
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define amdgpu_kernel void @force_align256(<64 x i32>) {
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%alloca = alloca i8, addrspace(5)
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store volatile i8 0, ptr addrspace(5) %alloca
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ret void
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}
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