Diana Picus a5cbd2ab0b Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039) ...

…133242)"

This reverts commit 130080fab1 because it
causes issues in testcases similar to coalescer_remat.ll [1], i.e. when
we use a VGPR tuple but only write to its lower parts. The high VGPRs
would then not be included in the vgpr_count, and accessing them would
be an out of bounds violation.

[1]
https://github.com/llvm/llvm-project/blob/main/llvm/test/CodeGen/AMDGPU/coalescer_remat.ll

2025-06-13 12:48:24 +02:00

..

AsmParser

[AMDGPU][True16][MC][CodeGen] true16 mode for v_cvt_pk_bf8/fp8_f32 (#141881)

2025-06-04 11:29:26 -04:00

Disassembler

[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)

2025-05-09 10:10:53 +01:00

MCA

[AMDGPU] Classify FLAT instructions as VMEM (#137148)

2025-05-07 09:20:52 +02:00

MCTargetDesc

Introduce MCAsmInfo::UsesSetToEquateSymbol and prefer = to .set

2025-06-11 22:19:31 -07:00

TargetInfo

…

Utils

[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)

2025-06-05 11:19:20 +02:00

AMDGPU.h

[AMDGPU] Move kernarg preload logic to separate pass (#130434)

2025-05-11 21:18:11 -07:00

AMDGPU.td

[AMDGPU][True16] set true16 mode as default on gfx110x (#140736)

2025-05-27 12:40:49 -04:00

AMDGPUAliasAnalysis.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUAliasAnalysis.h

…

AMDGPUAlwaysInlinePass.cpp

[NFC][AMDGPU] Replace direct arch comparison with isAMDGCN() (#131357)

2025-03-14 14:21:44 -04:00

AMDGPUAnnotateKernelFeatures.cpp

[AMDGPU] Remove the AnnotateKernelFeatures pass (#130198)

2025-04-15 15:17:33 -07:00

AMDGPUAnnotateUniformValues.cpp

[AMDGPU] Preserve all analyses if nothing changed (#117994)

2024-11-28 14:33:05 +00:00

AMDGPUArgumentUsageInfo.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

AMDGPUArgumentUsageInfo.h

[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)

2025-01-10 11:39:02 -08:00

AMDGPUAsanInstrumentation.cpp

[IRBuilder] Add new overload for CreateIntrinsic (#131942)

2025-03-31 08:10:34 -07:00

AMDGPUAsanInstrumentation.h

…

AMDGPUAsmPrinter.cpp

Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)

2025-06-13 12:48:24 +02:00

AMDGPUAsmPrinter.h

Register assembly printer passes (#138348)

2025-05-06 18:01:17 -07:00

AMDGPUAtomicOptimizer.cpp

[IRBuilder] Add new overload for CreateIntrinsic (#131942)

2025-03-31 08:10:34 -07:00

AMDGPUAttributes.def

Reapply "[AMDGPU] Infer amdgpu-no-flat-scratch-init attribute in AMDGPUAttributor (#94647)" (#118907)

2024-12-09 16:44:48 -08:00

AMDGPUAttributor.cpp

[IPO] Teach AbstractAttribute::getName to return StringRef (NFC) (#141313)

2025-05-23 23:58:49 -07:00

AMDGPUCallingConv.td

[AMDGPU] Change SGPR layout to striped caller/callee saved (#127353)

2025-03-08 09:28:20 -05:00

AMDGPUCallLowering.cpp

[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)

2025-06-05 11:19:20 +02:00

AMDGPUCallLowering.h

…

AMDGPUCodeGenPrepare.cpp

[ValueTracking] Make Depth last default arg (NFC) (#142384)

2025-06-03 17:12:24 +01:00

AMDGPUCombine.td

[AMDGPU] Canonicalize G_ZEXT of the shift amount in RegBankCombiner (#131792)

2025-05-14 10:48:51 +02:00

AMDGPUCombinerHelper.cpp

[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)

2025-03-29 11:51:29 +01:00

AMDGPUCombinerHelper.h

[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)

2025-03-29 11:51:29 +01:00

AMDGPUCtorDtorLowering.cpp

…

AMDGPUCtorDtorLowering.h

…

AMDGPUExportClustering.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUExportClustering.h

…

AMDGPUExportKernelRuntimeHandles.cpp

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUExportKernelRuntimeHandles.h

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUFeatures.td

AMDGPU: Increase the LDS size to support to 160 KB for gfx950 (#116309)

2024-11-18 10:48:56 -08:00

AMDGPUFrameLowering.cpp

…

AMDGPUFrameLowering.h

…

AMDGPUGenRegisterBankInfo.def

…

AMDGPUGISel.td

AMDGPU: Add v_permlane16_swap_b32 and v_permlane32_swap_b32 for gfx950 (#117260)

2024-11-22 20:12:50 -08:00

AMDGPUGlobalISelDivergenceLowering.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUGlobalISelUtils.cpp

[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)

2025-03-29 11:51:29 +01:00

AMDGPUGlobalISelUtils.h

[GlobalISel][NFC] Rename GISelKnownBits to GISelValueTracking (#133466)

2025-03-29 11:51:29 +01:00

AMDGPUHSAMetadataStreamer.cpp

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUHSAMetadataStreamer.h

AMDGPU: Move enqueued block handling into clang (#128519)

2025-03-10 19:54:04 +07:00

AMDGPUIGroupLP.cpp

Revert "[llvm][NFC] Use llvm::sort()" (#140668)

2025-05-20 11:27:03 +08:00

AMDGPUIGroupLP.h

…

AMDGPUImageIntrinsicOptimizer.cpp

[AMDGPU] Change placeholder from undef to poison (#130853)

2025-03-12 12:52:38 +00:00

AMDGPUInsertDelayAlu.cpp

[llvm] Use *Set::insert_range (NFC) (#132509)

2025-03-22 08:07:33 -07:00

AMDGPUInstCombineIntrinsic.cpp

[AMDGPU] Detect trivially uniform arguments in InstCombine (#129897)

2025-06-09 12:06:03 +01:00

AMDGPUInstrInfo.cpp

[AMDGPU] Use variadic isa<>. NFC. (#137016)

2025-04-24 08:19:09 +01:00

AMDGPUInstrInfo.h

…

AMDGPUInstrInfo.td

[AMDGPU] Dynamic VGPR support for llvm.amdgcn.cs.chain (#130094)

2025-03-20 08:38:04 +01:00

AMDGPUInstructions.td

[AMDGPU] Simplify definition of AddrSpaces. NFC. (#141030)

2025-05-22 11:14:16 +01:00

AMDGPUInstructionSelector.cpp

Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)

2025-05-28 12:26:39 -07:00

AMDGPUInstructionSelector.h

Revert "[AMDGPU] Implement vop3p complex pattern optmization for gisel" (#136249)

2025-04-17 23:45:30 -04:00

AMDGPUISelDAGToDAG.cpp

[AMDGPU][True16][CodeGen] optimize codegen for mad-mix in true16 (#124995)

2025-05-05 23:08:03 -04:00

AMDGPUISelDAGToDAG.h

[AMDGPU] Add intrinsics and MIs for ds_bvh_stack_* (#130007)

2025-03-17 09:13:20 +01:00

AMDGPUISelLowering.cpp

[AMDGPU] Convert more 64-bit lshr to 32-bit if shift amt>=32 (#138204)

2025-06-13 17:03:06 +09:00

AMDGPUISelLowering.h

AMDGPU][True16][CodeGen] FP_Round f64 to f16 in true16 (#128911)

2025-05-08 13:30:09 -04:00

AMDGPULateCodeGenPrepare.cpp

[ValueTracking] Make Depth last default arg (NFC) (#142384)

2025-06-03 17:12:24 +01:00

AMDGPULegalizerInfo.cpp

[llvm] Compare std::optional<T> to values directly (NFC) (#143340)

2025-06-08 22:37:59 -07:00

AMDGPULegalizerInfo.h

[AMDGPU] Support image_bvh8_intersect_ray instruction and intrinsic. (#130041)

2025-03-19 16:08:08 +01:00

AMDGPULibCalls.cpp

[ValueTracking] Make Depth last default arg (NFC) (#142384)

2025-06-03 17:12:24 +01:00

AMDGPULibFunc.cpp

[AMDGPU] Provide default value in get intrinsic param type (#122448)

2025-01-10 15:29:42 +01:00

AMDGPULibFunc.h

AMDGPU: Verify function type matches when matching libcalls (#119043)

2024-12-16 15:01:48 +09:00

AMDGPULowerBufferFatPointers.cpp

[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)

2025-06-12 11:51:58 +01:00

AMDGPULowerKernelArguments.cpp

[AMDGPU] Move kernarg preload logic to separate pass (#130434)

2025-05-11 21:18:11 -07:00

AMDGPULowerKernelAttributes.cpp

[AMDGPU] Add a new function getIntegerPairAttribute (#133271)

2025-03-27 15:38:54 -04:00

AMDGPULowerModuleLDSPass.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUMachineFunction.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

AMDGPUMachineFunction.h

…

AMDGPUMachineModuleInfo.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUMachineModuleInfo.h

…

AMDGPUMacroFusion.cpp

…

AMDGPUMacroFusion.h

[CodeGen] Move MISched target hooks into TargetMachine (#125700)

2025-02-05 11:41:37 +05:30

AMDGPUMarkLastScratchLoad.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUMCInstLower.cpp

Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)

2025-04-25 11:29:27 +02:00

AMDGPUMCInstLower.h

[AMDGPU][True16][CodeGen] reopen "FLAT_load using D16 pseudo instruction" (#127673)

2025-02-18 18:16:23 -05:00

AMDGPUMCResourceInfo.cpp

[AMDGPU] Flatten recursive register resource info propagation (#142766)

2025-06-12 14:35:28 +01:00

AMDGPUMCResourceInfo.h

[AMDGPU] Flatten recursive register resource info propagation (#142766)

2025-06-12 14:35:28 +01:00

AMDGPUMemoryUtils.cpp

[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)

2025-06-05 11:19:20 +02:00

AMDGPUMemoryUtils.h

…

AMDGPUMIRFormatter.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

AMDGPUMIRFormatter.h

…

AMDGPUPassRegistry.def

[AMDGPU] Move kernarg preload logic to separate pass (#130434)

2025-05-11 21:18:11 -07:00

AMDGPUPerfHintAnalysis.cpp

…

AMDGPUPerfHintAnalysis.h

…

AMDGPUPostLegalizerCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPUPredicateControl.td

…

AMDGPUPreLegalizerCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPUPreloadKernArgProlog.cpp

[AMDGPU][NPM] Cleanup AMDGPUPassRegistry.def (#130071)

2025-04-17 10:08:22 +05:30

AMDGPUPreloadKernArgProlog.h

[AMDGPU] Add backward compatibility layer for kernarg preloading (#119167)

2025-01-10 11:39:02 -08:00

AMDGPUPreloadKernelArguments.cpp

[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)

2025-06-12 11:51:58 +01:00

AMDGPUPrintfRuntimeBinding.cpp

Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)

2025-05-28 12:26:39 -07:00

AMDGPUPromoteAlloca.cpp

[AMDGPU] Promote nestedGEP allocas to vectors (#141199)

2025-06-02 16:20:14 +08:00

AMDGPUPromoteKernelArguments.cpp

…

AMDGPUPTNote.h

…

AMDGPURegBankCombiner.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPURegBankLegalize.cpp

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

AMDGPURegBankLegalizeHelper.cpp

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

AMDGPURegBankLegalizeHelper.h

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

AMDGPURegBankLegalizeRules.cpp

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

AMDGPURegBankLegalizeRules.h

AMDGPU/GlobalISel: add RegBankLegalize rules for bit shifts and sext-inreg (#132385)

2025-05-26 12:16:46 +02:00

AMDGPURegBankSelect.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

AMDGPURegisterBankInfo.cpp

[AMDGPU] Add a new amdgcn.load.to.lds intrinsic (#137425)

2025-05-19 07:15:04 -07:00

AMDGPURegisterBankInfo.h

…

AMDGPURegisterBanks.td

[AMDGPU][True16][CodeGen] uaddsat/usubsat true16 selection in gisel (#128233)

2025-02-25 17:09:34 -05:00

AMDGPURemoveIncompatibleFunctions.cpp

[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)

2025-01-13 10:11:40 +05:30

AMDGPURemoveIncompatibleFunctions.h

[AMDGPU][NewPM] Port AMDGPURemoveIncompatibleFunctions to NPM (#122261)

2025-01-13 10:11:40 +05:30

AMDGPUReserveWWMRegs.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUReserveWWMRegs.h

[AMDGPU][NewPM] Port AMDGPUReserveWWMRegs to NPM (#123722)

2025-03-10 17:36:35 +05:30

AMDGPUResourceUsageAnalysis.cpp

Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)

2025-06-13 12:48:24 +02:00

AMDGPUResourceUsageAnalysis.h

…

AMDGPURewriteOutArguments.cpp

[DebugInfo][RemoveDIs] Delete debug-info-format flag (#143746)

2025-06-12 11:51:58 +01:00

AMDGPURewriteUndefForPHI.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUSearchableTables.td

[AMDGPU] Add llvm.amdgcn.dead intrinsic (#123190)

2025-02-20 09:25:48 +01:00

AMDGPUSelectionDAGInfo.cpp

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AMDGPUSelectionDAGInfo.h

[SelectionDAG] Virtualize isTargetStrictFPOpcode / isTargetMemoryOpcode (#119969)

2024-12-21 05:29:51 +03:00

AMDGPUSetWavePriority.cpp

[AMDGPU] AMDGPUSetWavePriority: Remove unused variable NFC (#134069)

2025-04-02 16:52:05 +05:30

AMDGPUSplitModule.cpp

[AMDGPU][SplitModule] Do not create empty modules (#135761)

2025-04-25 09:36:41 +02:00

AMDGPUSplitModule.h

…

AMDGPUSubtarget.cpp

[AMDGPU] Fix computation of waves/EU maximum (#140921)

2025-05-22 02:45:59 +02:00

AMDGPUSubtarget.h

[AMDGPU][Attributor] Rework update of AAAMDWavesPerEU (#123995)

2025-05-17 01:01:09 -04:00

AMDGPUSwLowerLDS.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

AMDGPUTargetMachine.cpp

[AMDGPU] Remove duplicated/confusing helpers. NFCI (#142598)

2025-06-05 11:19:20 +02:00

AMDGPUTargetMachine.h

[CodeGen][NPM] Port VirtRegRewriter to NPM (#130564)

2025-04-30 14:10:46 +05:30

AMDGPUTargetObjectFile.cpp

…

AMDGPUTargetObjectFile.h

…

AMDGPUTargetTransformInfo.cpp

[ValueTracking] Make Depth last default arg (NFC) (#142384)

2025-06-03 17:12:24 +01:00

AMDGPUTargetTransformInfo.h

[AMDGPU] Hoist readlane/readfirstlane through unary/binary operands (#129037)

2025-05-13 12:00:49 +02:00

AMDGPUUnifyDivergentExitNodes.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

AMDGPUUnifyDivergentExitNodes.h

…

AMDGPUUnifyMetadata.cpp

…

AMDGPUWaitSGPRHazards.cpp

[llvm] Use llvm::any_of (NFC) (#141444)

2025-05-26 09:13:21 -07:00

AMDGPUWaitSGPRHazards.h

[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)

2025-01-30 11:21:11 +09:00

AMDKernelCodeT.h

…

BUFInstructions.td

[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)

2025-04-28 09:26:34 -07:00

CaymanInstructions.td

…

CMakeLists.txt

[AMDGPU] Move kernarg preload logic to separate pass (#130434)

2025-05-11 21:18:11 -07:00

DSDIRInstructions.td

[AMDGPU] New GFX12 aliases lds_direct_load and lds_param_load (#119205)

2024-12-09 14:15:56 +00:00

DSInstructions.td

[Targets] Migrate from atomic_load_8/16/32/64 to atomic_load_nonext_8/16/32/64. NFC (#137428)

2025-04-28 09:26:34 -07:00

EvergreenInstructions.td

…

EXPInstructions.td

…

FLATInstructions.td

[AMDGPU][True16][CodeGen] atomic load/store i8 in true16 mode (#143044)

2025-06-09 15:05:06 -04:00

GCNCreateVOPD.cpp

[AMDGPU][NPM] Port GCNCreateVOPD to NPM (#130059)

2025-03-14 10:22:45 +05:30

GCNDPPCombine.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

GCNDPPCombine.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

GCNHazardRecognizer.cpp

[AMDGPU] Support bottom-up postRA scheduing. (#135295)

2025-06-05 22:07:06 +08:00

GCNHazardRecognizer.h

[AMDGPU] Rewrite GFX12 SGPR hazard handling to dedicated pass (#118750)

2025-01-30 11:21:11 +09:00

GCNILPSched.cpp

…

GCNIterativeScheduler.cpp

Revert "[AMDGPU] Extend test coverage for cross RC register coalescing (#132137)"

2025-05-05 16:33:18 -07:00

GCNIterativeScheduler.h

[AMDGPU] Teach iterative schedulers about IGLP (#134953)

2025-04-11 15:34:49 -07:00

GCNMinRegStrategy.cpp

…

GCNNSAReassign.cpp

[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)

2025-02-18 11:13:31 +05:30

GCNNSAReassign.h

[AMDGPU][NewPM] Port GCNNSAReassign pass to new pass manager (#125034)

2025-02-18 11:13:31 +05:30

GCNPreRALongBranchReg.cpp

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRALongBranchReg.h

[CodeGen][NewPM] Port GCNPreRALongBranchReg to NPM. (#125844)

2025-02-05 18:46:27 +05:30

GCNPreRAOptimizations.cpp

[AMDGPU][True16][CodeGen] update test for buildbot failure (#131028)

2025-03-12 16:59:48 -04:00

GCNPreRAOptimizations.h

[AMDGPU][NewPM] Port "GCNPreRAOptimizations" pass to NPM (#126040)

2025-02-11 11:09:38 +05:30

GCNProcessors.td

[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)

2025-02-19 10:20:48 +01:00

GCNRegPressure.cpp

[AMDGPU] Simplify GCNRegPressure::RegKind (NFC) (#142682)

2025-06-04 11:23:57 +02:00

GCNRegPressure.h

[AMDGPU] Simplify GCNRegPressure::RegKind (NFC) (#142682)

2025-06-04 11:23:57 +02:00

GCNRewritePartialRegUses.cpp

[AMDGPU] Simplify GCNRewritePartialRegUses pass. (#135199)

2025-04-11 15:45:24 +02:00

GCNRewritePartialRegUses.h

[AMDGPU][NewPM] Port "GCNRewritePartialRegUses" pass to NPM (#126024)

2025-02-12 11:21:40 +05:30

GCNSchedStrategy.cpp

Fix two instances of -Wparentheses warnings [NFC]

2025-06-12 09:43:30 +02:00

GCNSchedStrategy.h

[AMDGPU][Scheduler] Delete RescheduleRegions bitvector from scheduler (NFC) (#141595)

2025-05-27 17:10:28 +02:00

GCNSubtarget.cpp

Reapply "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#125885)" (#139548)

2025-05-13 11:11:00 +02:00

GCNSubtarget.h

Reapply "[AMDGPU][Scheduler] Refactor ArchVGPR rematerialization during scheduling (#125885)" (#139548)

2025-05-13 11:11:00 +02:00

GCNVOPDUtils.cpp

…

GCNVOPDUtils.h

…

InstCombineTables.td

…

MIMGInstructions.td

[AMDGPU] Add support for point sample accel out of order returns (#127991)

2025-04-10 15:33:48 +01:00

R600.h

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600.td

…

R600AsmPrinter.cpp

…

R600AsmPrinter.h

[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel

2025-03-29 11:08:13 -07:00

R600ClauseMergePass.cpp

…

R600ControlFlowFinalizer.cpp

…

R600Defines.h

…

R600EmitClauseMarkers.cpp

[NFC][LLVM][AMDGPU] Cleanup pass initialization for AMDGPU (#134410)

2025-04-07 17:27:50 -07:00

R600ExpandSpecialInstrs.cpp

[TableGen] Emit OpName as an enum class instead of a namespace (#125313)

2025-02-12 08:19:30 -08:00

R600FrameLowering.cpp

…

R600FrameLowering.h

…

R600InstrFormats.td

…

R600InstrInfo.cpp

[MC] Return MCRegister from MCRegisterClass::getRegister. NFC (#132126)

2025-03-20 07:24:53 -07:00

R600InstrInfo.h

[CodeGen] Change copyPhysReg interface to use Register instead of MCRegister. (#128473)

2025-02-24 09:55:34 -08:00

R600InstrInfo.td

…

R600Instructions.td

…

R600ISelDAGToDAG.cpp

[AMDGPU] Remove unused includes (NFC) (#141376)

2025-05-24 14:48:46 -07:00

R600ISelLowering.cpp

[Target] Remove unused local variables (NFC) (#138443)

2025-05-04 07:56:38 -07:00

R600ISelLowering.h

…

R600MachineCFGStructurizer.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

R600MachineFunctionInfo.cpp

…

R600MachineFunctionInfo.h

…

R600MachineScheduler.cpp

…

R600MachineScheduler.h

…

R600MCInstLower.cpp

[RISCV] Replace @plt/@gotpcrel in data directives with %pltpcrel %gotpcrel

2025-03-29 11:08:13 -07:00

R600OpenCLImageTypeLoweringPass.cpp

…

R600OptimizeVectorRegisters.cpp

[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

2025-06-04 12:30:56 -07:00

R600Packetizer.cpp

[TableGen] Emit OpName as an enum class instead of a namespace (#125313)

2025-02-12 08:19:30 -08:00

R600Processors.td

…

R600RegisterInfo.cpp

…

R600RegisterInfo.h

…

R600RegisterInfo.td

…

R600Schedule.td

…

R600Subtarget.cpp

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16 15:13:46 +03:00

R600Subtarget.h

[SelectionDAG] Add empty implementation of SelectionDAGInfo to some targets (#119968)

2024-12-16 15:13:46 +03:00

R600TargetMachine.cpp

[TTI] Simplify implementation (NFCI) (#136674)

2025-04-26 15:25:40 +03:00

R600TargetMachine.h

[CodeGen] Move MISched target hooks into TargetMachine (#125700)

2025-02-05 11:41:37 +05:30

R600TargetTransformInfo.cpp

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R600TargetTransformInfo.h

[CostModel] Make Op0 and Op1 const in getVectorInstrCost. NFC (#137631)

2025-05-01 15:55:08 +01:00

R700Instructions.td

…

SIAnnotateControlFlow.cpp

AMDGPU: Rename variable from undef to poison (#130460)

2025-03-10 22:18:36 +07:00

SIDefines.h

[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)

2025-05-09 10:10:53 +01:00

SIFixSGPRCopies.cpp

[AMDGPU] Fix SIFixSGPRCopies handling of STRICT_WWM and friends (#142122)

2025-05-30 16:32:56 +01:00

SIFixSGPRCopies.h

…

SIFixVGPRCopies.cpp

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFixVGPRCopies.h

[AMDGPU][NewPM] Port SIFixVGPRCopies to NPM (#123592)

2025-01-21 15:27:46 +05:30

SIFoldOperands.cpp

AMDGPU: Try constant fold after folding immediate (#141862)

2025-06-10 11:44:44 +09:00

SIFoldOperands.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIFormMemoryClauses.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIFormMemoryClauses.h

[AMDGPU][NewPM] Port "SIFormMemoryClauses" to NPM (#127181)

2025-02-17 11:07:17 +05:30

SIFrameLowering.cpp

[llvm] Use llvm::is_sorted (NFC) (#140399)

2025-05-17 14:29:35 -07:00

SIFrameLowering.h

Reland [AMDGPU] Support block load/store for CSR #130013 (#137169)

2025-04-25 11:29:27 +02:00

SIInsertHardClauses.cpp

[AMDGPU] SIInsertHardClause: add configurable clause length limit (#142343)

2025-06-04 15:00:34 +09:00

SIInsertWaitcnts.cpp

[AMDGPU] Treat image_msaa_load as a sampler operation (#141726)

2025-05-28 19:56:05 +09:00

SIInstrFormats.td

AMDGPU: Define v_mfma_f32_{16x16x128|32x32x64}_f8f6f4 instructions (#116723)

2024-11-21 08:51:58 -08:00

SIInstrInfo.cpp

[AMDGPU][True16][CodeGen] v_s_xxx_f16 t16 mode handling in movetoVALU process (#141152)

2025-06-10 15:36:44 -04:00

SIInstrInfo.h

[AMDGPU][True16][CodeGen] legalize 16bit and 32bit use-def chain for moveToVALU in si-fix-sgpr-lowering (#138734)

2025-06-04 09:53:10 -04:00

SIInstrInfo.td

[AMDGPU][True16] remove AsmVOP3OpSel (#143465)

2025-06-10 22:49:09 -04:00

SIInstructions.td

[AMDGPU] Patterns for <2 x bfloat> fneg (fabs) (#142911)

2025-06-05 10:00:24 -07:00

SIISelLowering.cpp

AMDGPU: Custom lower fptrunc vectors for f32 -> f16 (#141883)

2025-06-06 15:15:24 -07:00

SIISelLowering.h

AMDGPU: Custom lower fptrunc vectors for f32 -> f16 (#141883)

2025-06-06 15:15:24 -07:00

SILateBranchLowering.cpp

[AMDGPU][NPM] Port SILateBranchLowering to NPM (#130063)

2025-03-26 19:28:19 +05:30

SILoadStoreOptimizer.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILoadStoreOptimizer.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerControlFlow.cpp

[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)

2025-01-16 11:06:38 +05:30

SILowerControlFlow.h

[AMDGPU][NewPM] Port SILowerControlFlow pass into NPM. (#123045)

2025-01-16 11:06:38 +05:30

SILowerI1Copies.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerI1Copies.h

AMDGPU/GlobalISel: Temporal divergence lowering (non i1) (#124298)

2025-03-12 12:09:37 +01:00

SILowerSGPRSpills.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerSGPRSpills.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SILowerWWMCopies.cpp

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SILowerWWMCopies.h

[AMDGPU][NewPM] Port SILowerWWMCopies to NPM (#123695)

2025-01-22 14:54:01 +05:30

SIMachineFunctionInfo.cpp

[AMDGPU] Use llvm::find and llvm::find_if (NFC) (#135582)

2025-04-13 23:46:57 -07:00

SIMachineFunctionInfo.h

Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)

2025-06-13 12:48:24 +02:00

SIMachineScheduler.cpp

[AMDGPU] Use MachineRegisterInfo::def_instructions (NFC) (#142782)

2025-06-04 12:30:56 -07:00

SIMachineScheduler.h

[AMDGPU] Replace unsigned with Register in SIMachineScheduler. NFC

2025-01-26 00:26:00 -08:00

SIMemoryLegalizer.cpp

Warn on misuse of DiagnosticInfo classes that hold Twines (#137397)

2025-05-28 12:26:39 -07:00

SIModeRegister.cpp

[AMDGPU][NPM] Port SIModeRegister to NPM (#129014)

2025-03-04 10:51:03 +05:30

SIModeRegisterDefaults.cpp

…

SIModeRegisterDefaults.h

…

SIOptimizeExecMasking.cpp

[AMDGPU][True16][CodeGen] True16 Add OpSel when optimizing exec mask (#128928)

2025-02-28 09:41:05 -05:00

SIOptimizeExecMasking.h

[AMDGPU][NewPM] Port SIOptimizeExecMasking to NPM (#123572)

2025-01-20 16:34:01 +05:30

SIOptimizeExecMaskingPreRA.cpp

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20 17:35:56 +05:30

SIOptimizeExecMaskingPreRA.h

[AMDGPU][NewPM] Port SIOptimizeExecMaskingPreRA to NPM (#125351)

2025-02-20 17:35:56 +05:30

SIOptimizeVGPRLiveRange.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIOptimizeVGPRLiveRange.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIPeepholeSDWA.cpp

[AMDGPU] si-peephole-sdwa: Remove dead code from createSDWAversion (#141462)

2025-05-26 15:28:03 +02:00

SIPeepholeSDWA.h

…

SIPostRABundler.cpp

AMDGPU: VIMAGE/VSAMPLE are bundle candidates (#140854)

2025-05-28 08:47:05 +08:00

SIPostRABundler.h

[AMDGPU][NewPM] Port SIPostRABundler to NPM (#123717)

2025-02-21 16:05:58 +05:30

SIPreAllocateWWMRegs.cpp

[AMDGPU] Remove unused includes (NFC) (#116154)

2024-11-13 21:10:03 -08:00

SIPreAllocateWWMRegs.h

…

SIPreEmitPeephole.cpp

[AMDGPU][NPM] Port SIPreEmitPeephole to NPM (#130065)

2025-04-08 17:58:48 +05:30

SIProgramInfo.cpp

[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)

2025-03-17 23:17:46 +00:00

SIProgramInfo.h

[llvm][AMDGPU] Enable FWD_PROGRESS bit for GFX10+ (#128367)

2025-03-17 23:17:46 +00:00

SIRegisterInfo.cpp

Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)

2025-06-13 12:48:24 +02:00

SIRegisterInfo.h

Revert "[AMDGPU] Skip register uses in AMDGPUResourceUsageAnalysis (#… (#144039)

2025-06-13 12:48:24 +02:00

SIRegisterInfo.td

[AMDGPU] using loop to define data type convert patterns (#132899)

2025-05-14 13:56:36 +08:00

SISchedule.td

[AMDGPU] Replace gfx940 and gfx941 with gfx942 in llvm (#126763)

2025-02-19 10:20:48 +01:00

SIShrinkInstructions.cpp

AMDGPU: Directly check if shrink-instructions run is post-RA (#142009)

2025-05-30 15:52:18 +02:00

SIShrinkInstructions.h

…

SIWholeQuadMode.cpp

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SIWholeQuadMode.h

[NFC][CodeGen] Adopt MachineFunctionProperties convenience accessors (#141101)

2025-05-23 08:30:29 -07:00

SMInstructions.td

[AMDGPU] Disallow null for more resource operands (#121941)

2025-01-08 08:02:10 +00:00

SOPInstructions.td

[AMDGPU] Add UniformBinFrag to SALU fminimum/fmaximum patterns. NFCI. (#142169)

2025-06-02 13:02:08 +01:00

VIInstrFormats.td

…

VINTERPInstructions.td

[AMDGPU][True16][CodeGen] support for true16 for vinterp 16bit instructions (#116702)

2024-12-09 11:52:05 -05:00

VOP1Instructions.td

[AMDGPU] Automate creation of byte_sel dags. NFCI. (#140155)

2025-05-16 08:54:04 -07:00

VOP2Instructions.td

[AMDGPU] Simplify getIns64. NFCI. (#139981)

2025-05-15 02:59:46 -07:00

VOP3Instructions.td

[AMDGPU][True16] remove AsmVOP3OpSel (#143465)

2025-06-10 22:49:09 -04:00

VOP3PInstructions.td

[AMDGPU][MC] Allow dpp in v_dot2_f32_bf16 for GFX11 and 12 (#142451)

2025-06-05 09:55:12 -07:00

VOPCInstructions.td

[AMDGPU][True16][MC] Generate op_sel operands for VOPC instructions (#125561)

2025-02-05 10:40:34 -05:00

VOPDInstructions.td

[AMDGPU][NFC] Remove _DEFERRED operands. (#139123)

2025-05-09 10:10:53 +01:00

VOPInstructions.td

[AMDGPU][True16] remove AsmVOP3OpSel (#143465)

2025-06-10 22:49:09 -04:00