87b8d94371
Fixed: 1. Maximum register pressure calculation at the instruction level. Previously max RP included both def and use of registers of an instruction. Now maximum RP includes _uses_ and _early-clobber defs_. 2. Uses were incorrectly tracked and this resulted in a mismatch of live-in set reported by LiveIntervals and tracked live reg set when the beginning of the block is reached. Interface has changed, moveMaxPressure becomes deprecated and getMaxPressure, resetMaxPressure functions are added. reset function seem now more consistent.
612 lines
19 KiB
C++
612 lines
19 KiB
C++
//===- GCNRegPressure.cpp -------------------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file implements the GCNRegPressure class.
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///
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//===----------------------------------------------------------------------===//
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#include "GCNRegPressure.h"
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#include "AMDGPU.h"
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#include "llvm/CodeGen/RegisterPressure.h"
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using namespace llvm;
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#define DEBUG_TYPE "machine-scheduler"
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bool llvm::isEqual(const GCNRPTracker::LiveRegSet &S1,
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const GCNRPTracker::LiveRegSet &S2) {
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if (S1.size() != S2.size())
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return false;
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for (const auto &P : S1) {
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auto I = S2.find(P.first);
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if (I == S2.end() || I->second != P.second)
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return false;
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}
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return true;
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRegPressure
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unsigned GCNRegPressure::getRegKind(Register Reg,
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const MachineRegisterInfo &MRI) {
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assert(Reg.isVirtual());
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const auto RC = MRI.getRegClass(Reg);
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auto STI = static_cast<const SIRegisterInfo*>(MRI.getTargetRegisterInfo());
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return STI->isSGPRClass(RC)
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? (STI->getRegSizeInBits(*RC) == 32 ? SGPR32 : SGPR_TUPLE)
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: STI->isAGPRClass(RC)
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? (STI->getRegSizeInBits(*RC) == 32 ? AGPR32 : AGPR_TUPLE)
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: (STI->getRegSizeInBits(*RC) == 32 ? VGPR32 : VGPR_TUPLE);
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}
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void GCNRegPressure::inc(unsigned Reg,
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LaneBitmask PrevMask,
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LaneBitmask NewMask,
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const MachineRegisterInfo &MRI) {
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if (SIRegisterInfo::getNumCoveredRegs(NewMask) ==
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SIRegisterInfo::getNumCoveredRegs(PrevMask))
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return;
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int Sign = 1;
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if (NewMask < PrevMask) {
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std::swap(NewMask, PrevMask);
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Sign = -1;
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}
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switch (auto Kind = getRegKind(Reg, MRI)) {
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case SGPR32:
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case VGPR32:
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case AGPR32:
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Value[Kind] += Sign;
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break;
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case SGPR_TUPLE:
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case VGPR_TUPLE:
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case AGPR_TUPLE:
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assert(PrevMask < NewMask);
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Value[Kind == SGPR_TUPLE ? SGPR32 : Kind == AGPR_TUPLE ? AGPR32 : VGPR32] +=
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Sign * SIRegisterInfo::getNumCoveredRegs(~PrevMask & NewMask);
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if (PrevMask.none()) {
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assert(NewMask.any());
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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Value[Kind] +=
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Sign * TRI->getRegClassWeight(MRI.getRegClass(Reg)).RegWeight;
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}
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break;
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default: llvm_unreachable("Unknown register kind");
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}
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}
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bool GCNRegPressure::less(const GCNSubtarget &ST,
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const GCNRegPressure& O,
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unsigned MaxOccupancy) const {
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const auto SGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(getSGPRNum()));
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const auto VGPROcc =
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std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(getVGPRNum(ST.hasGFX90AInsts())));
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const auto OtherSGPROcc = std::min(MaxOccupancy,
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ST.getOccupancyWithNumSGPRs(O.getSGPRNum()));
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const auto OtherVGPROcc =
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std::min(MaxOccupancy,
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ST.getOccupancyWithNumVGPRs(O.getVGPRNum(ST.hasGFX90AInsts())));
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const auto Occ = std::min(SGPROcc, VGPROcc);
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const auto OtherOcc = std::min(OtherSGPROcc, OtherVGPROcc);
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if (Occ != OtherOcc)
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return Occ > OtherOcc;
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bool SGPRImportant = SGPROcc < VGPROcc;
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const bool OtherSGPRImportant = OtherSGPROcc < OtherVGPROcc;
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// if both pressures disagree on what is more important compare vgprs
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if (SGPRImportant != OtherSGPRImportant) {
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SGPRImportant = false;
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}
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// compare large regs pressure
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bool SGPRFirst = SGPRImportant;
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for (int I = 2; I > 0; --I, SGPRFirst = !SGPRFirst) {
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if (SGPRFirst) {
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auto SW = getSGPRTuplesWeight();
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auto OtherSW = O.getSGPRTuplesWeight();
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if (SW != OtherSW)
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return SW < OtherSW;
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} else {
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auto VW = getVGPRTuplesWeight();
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auto OtherVW = O.getVGPRTuplesWeight();
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if (VW != OtherVW)
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return VW < OtherVW;
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}
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}
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return SGPRImportant ? (getSGPRNum() < O.getSGPRNum()):
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(getVGPRNum(ST.hasGFX90AInsts()) <
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O.getVGPRNum(ST.hasGFX90AInsts()));
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}
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Printable llvm::print(const GCNRegPressure &RP, const GCNSubtarget *ST) {
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return Printable([&RP, ST](raw_ostream &OS) {
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OS << "VGPRs: " << RP.Value[GCNRegPressure::VGPR32] << ' '
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<< "AGPRs: " << RP.getAGPRNum();
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if (ST)
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OS << "(O"
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<< ST->getOccupancyWithNumVGPRs(RP.getVGPRNum(ST->hasGFX90AInsts()))
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<< ')';
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OS << ", SGPRs: " << RP.getSGPRNum();
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if (ST)
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OS << "(O" << ST->getOccupancyWithNumSGPRs(RP.getSGPRNum()) << ')';
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OS << ", LVGPR WT: " << RP.getVGPRTuplesWeight()
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<< ", LSGPR WT: " << RP.getSGPRTuplesWeight();
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if (ST)
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OS << " -> Occ: " << RP.getOccupancy(*ST);
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OS << '\n';
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});
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}
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static LaneBitmask getDefRegMask(const MachineOperand &MO,
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const MachineRegisterInfo &MRI) {
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assert(MO.isDef() && MO.isReg() && MO.getReg().isVirtual());
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// We don't rely on read-undef flag because in case of tentative schedule
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// tracking it isn't set correctly yet. This works correctly however since
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// use mask has been tracked before using LIS.
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return MO.getSubReg() == 0 ?
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MRI.getMaxLaneMaskForVReg(MO.getReg()) :
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MRI.getTargetRegisterInfo()->getSubRegIndexLaneMask(MO.getSubReg());
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}
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static void
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collectVirtualRegUses(SmallVectorImpl<RegisterMaskPair> &RegMaskPairs,
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const MachineInstr &MI, const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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SlotIndex InstrSI;
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for (const auto &MO : MI.operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (!MO.isUse() || !MO.readsReg())
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continue;
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Register Reg = MO.getReg();
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if (llvm::any_of(RegMaskPairs, [Reg](const RegisterMaskPair &RM) {
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return RM.RegUnit == Reg;
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}))
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continue;
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LaneBitmask UseMask;
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auto &LI = LIS.getInterval(Reg);
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if (!LI.hasSubRanges())
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UseMask = MRI.getMaxLaneMaskForVReg(Reg);
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else {
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// For a tentative schedule LIS isn't updated yet but livemask should
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// remain the same on any schedule. Subreg defs can be reordered but they
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// all must dominate uses anyway.
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if (!InstrSI)
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InstrSI = LIS.getInstructionIndex(*MO.getParent()).getBaseIndex();
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UseMask = getLiveLaneMask(LI, InstrSI, MRI);
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}
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RegMaskPairs.emplace_back(Reg, UseMask);
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}
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}
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///////////////////////////////////////////////////////////////////////////////
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// GCNRPTracker
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LaneBitmask llvm::getLiveLaneMask(unsigned Reg, SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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return getLiveLaneMask(LIS.getInterval(Reg), SI, MRI);
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}
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LaneBitmask llvm::getLiveLaneMask(const LiveInterval &LI, SlotIndex SI,
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const MachineRegisterInfo &MRI) {
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LaneBitmask LiveMask;
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if (LI.hasSubRanges()) {
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for (const auto &S : LI.subranges())
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if (S.liveAt(SI)) {
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LiveMask |= S.LaneMask;
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assert(LiveMask == (LiveMask & MRI.getMaxLaneMaskForVReg(LI.reg())));
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}
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} else if (LI.liveAt(SI)) {
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LiveMask = MRI.getMaxLaneMaskForVReg(LI.reg());
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}
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return LiveMask;
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}
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GCNRPTracker::LiveRegSet llvm::getLiveRegs(SlotIndex SI,
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const LiveIntervals &LIS,
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const MachineRegisterInfo &MRI) {
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GCNRPTracker::LiveRegSet LiveRegs;
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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auto Reg = Register::index2VirtReg(I);
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if (!LIS.hasInterval(Reg))
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continue;
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auto LiveMask = getLiveLaneMask(Reg, SI, LIS, MRI);
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if (LiveMask.any())
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LiveRegs[Reg] = LiveMask;
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}
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return LiveRegs;
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}
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void GCNRPTracker::reset(const MachineInstr &MI,
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const LiveRegSet *LiveRegsCopy,
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bool After) {
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const MachineFunction &MF = *MI.getMF();
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MRI = &MF.getRegInfo();
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if (LiveRegsCopy) {
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if (&LiveRegs != LiveRegsCopy)
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LiveRegs = *LiveRegsCopy;
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} else {
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LiveRegs = After ? getLiveRegsAfter(MI, LIS)
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: getLiveRegsBefore(MI, LIS);
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}
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MaxPressure = CurPressure = getRegPressure(*MRI, LiveRegs);
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}
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////////////////////////////////////////////////////////////////////////////////
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// GCNUpwardRPTracker
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void GCNUpwardRPTracker::reset(const MachineRegisterInfo &MRI_,
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const LiveRegSet &LiveRegs_) {
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MRI = &MRI_;
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LiveRegs = LiveRegs_;
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LastTrackedMI = nullptr;
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MaxPressure = CurPressure = getRegPressure(MRI_, LiveRegs_);
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}
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void GCNUpwardRPTracker::recede(const MachineInstr &MI) {
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assert(MRI && "call reset first");
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LastTrackedMI = &MI;
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if (MI.isDebugInstr())
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return;
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auto DecrementDef = [this](const MachineOperand &MO) {
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Register Reg = MO.getReg();
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auto I = LiveRegs.find(Reg);
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if (I == LiveRegs.end())
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return;
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LaneBitmask &LiveMask = I->second;
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LaneBitmask PrevMask = LiveMask;
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LiveMask &= ~getDefRegMask(MO, *MRI);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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if (LiveMask.none())
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LiveRegs.erase(I);
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};
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// Decrement non-early-clobber defs.
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SmallVector<const MachineOperand *, 2> EarlyClobberDefs;
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for (const MachineOperand &MO : MI.all_defs()) {
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if (!MO.getReg().isVirtual())
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continue;
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if (!MO.isEarlyClobber())
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DecrementDef(MO);
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else
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EarlyClobberDefs.push_back(&MO);
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}
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// Increment uses.
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SmallVector<RegisterMaskPair, 8> RegUses;
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collectVirtualRegUses(RegUses, MI, LIS, *MRI);
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for (const RegisterMaskPair &U : RegUses) {
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LaneBitmask &LiveMask = LiveRegs[U.RegUnit];
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LaneBitmask PrevMask = LiveMask;
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LiveMask |= U.LaneMask;
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CurPressure.inc(U.RegUnit, PrevMask, LiveMask, *MRI);
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}
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// Point of maximum pressure: non-early-clobber defs are decremented and uses
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// are incremented.
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MaxPressure = max(CurPressure, MaxPressure);
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// Now decrement early clobber defs.
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for (const MachineOperand *MO : EarlyClobberDefs)
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DecrementDef(*MO);
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assert(CurPressure == getRegPressure(*MRI, LiveRegs));
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}
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////////////////////////////////////////////////////////////////////////////////
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// GCNDownwardRPTracker
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bool GCNDownwardRPTracker::reset(const MachineInstr &MI,
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const LiveRegSet *LiveRegsCopy) {
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MRI = &MI.getParent()->getParent()->getRegInfo();
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LastTrackedMI = nullptr;
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MBBEnd = MI.getParent()->end();
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NextMI = &MI;
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NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
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if (NextMI == MBBEnd)
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return false;
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GCNRPTracker::reset(*NextMI, LiveRegsCopy, false);
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return true;
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}
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bool GCNDownwardRPTracker::advanceBeforeNext() {
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assert(MRI && "call reset first");
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if (!LastTrackedMI)
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return NextMI == MBBEnd;
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assert(NextMI == MBBEnd || !NextMI->isDebugInstr());
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SlotIndex SI = NextMI == MBBEnd
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? LIS.getInstructionIndex(*LastTrackedMI).getDeadSlot()
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: LIS.getInstructionIndex(*NextMI).getBaseIndex();
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assert(SI.isValid());
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// Remove dead registers or mask bits.
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SmallSet<Register, 8> SeenRegs;
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for (auto &MO : LastTrackedMI->operands()) {
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if (!MO.isReg() || !MO.getReg().isVirtual())
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continue;
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if (MO.isUse() && !MO.readsReg())
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continue;
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if (!SeenRegs.insert(MO.getReg()).second)
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continue;
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const LiveInterval &LI = LIS.getInterval(MO.getReg());
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if (LI.hasSubRanges()) {
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auto It = LiveRegs.end();
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for (const auto &S : LI.subranges()) {
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if (!S.liveAt(SI)) {
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if (It == LiveRegs.end()) {
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It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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}
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auto PrevMask = It->second;
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It->second &= ~S.LaneMask;
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CurPressure.inc(MO.getReg(), PrevMask, It->second, *MRI);
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}
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}
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if (It != LiveRegs.end() && It->second.none())
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LiveRegs.erase(It);
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} else if (!LI.liveAt(SI)) {
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auto It = LiveRegs.find(MO.getReg());
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if (It == LiveRegs.end())
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llvm_unreachable("register isn't live");
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CurPressure.inc(MO.getReg(), It->second, LaneBitmask::getNone(), *MRI);
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LiveRegs.erase(It);
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}
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}
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MaxPressure = max(MaxPressure, CurPressure);
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LastTrackedMI = nullptr;
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return NextMI == MBBEnd;
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}
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void GCNDownwardRPTracker::advanceToNext() {
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LastTrackedMI = &*NextMI++;
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NextMI = skipDebugInstructionsForward(NextMI, MBBEnd);
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// Add new registers or mask bits.
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for (const auto &MO : LastTrackedMI->all_defs()) {
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Register Reg = MO.getReg();
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if (!Reg.isVirtual())
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continue;
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auto &LiveMask = LiveRegs[Reg];
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auto PrevMask = LiveMask;
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LiveMask |= getDefRegMask(MO, *MRI);
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CurPressure.inc(Reg, PrevMask, LiveMask, *MRI);
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}
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MaxPressure = max(MaxPressure, CurPressure);
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}
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bool GCNDownwardRPTracker::advance() {
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if (NextMI == MBBEnd)
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return false;
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advanceBeforeNext();
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advanceToNext();
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return true;
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}
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bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator End) {
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while (NextMI != End)
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if (!advance()) return false;
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return true;
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}
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bool GCNDownwardRPTracker::advance(MachineBasicBlock::const_iterator Begin,
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MachineBasicBlock::const_iterator End,
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const LiveRegSet *LiveRegsCopy) {
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reset(*Begin, LiveRegsCopy);
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return advance(End);
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}
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Printable llvm::reportMismatch(const GCNRPTracker::LiveRegSet &LISLR,
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const GCNRPTracker::LiveRegSet &TrackedLR,
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const TargetRegisterInfo *TRI, StringRef Pfx) {
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return Printable([&LISLR, &TrackedLR, TRI, Pfx](raw_ostream &OS) {
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for (auto const &P : TrackedLR) {
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auto I = LISLR.find(P.first);
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if (I == LISLR.end()) {
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OS << Pfx << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
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<< " isn't found in LIS reported set\n";
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} else if (I->second != P.second) {
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OS << Pfx << printReg(P.first, TRI)
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<< " masks doesn't match: LIS reported " << PrintLaneMask(I->second)
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<< ", tracked " << PrintLaneMask(P.second) << '\n';
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}
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}
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for (auto const &P : LISLR) {
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auto I = TrackedLR.find(P.first);
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if (I == TrackedLR.end()) {
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OS << Pfx << printReg(P.first, TRI) << ":L" << PrintLaneMask(P.second)
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<< " isn't found in tracked set\n";
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}
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}
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});
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}
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bool GCNUpwardRPTracker::isValid() const {
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const auto &SI = LIS.getInstructionIndex(*LastTrackedMI).getBaseIndex();
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const auto LISLR = llvm::getLiveRegs(SI, LIS, *MRI);
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const auto &TrackedLR = LiveRegs;
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if (!isEqual(LISLR, TrackedLR)) {
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dbgs() << "\nGCNUpwardRPTracker error: Tracked and"
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" LIS reported livesets mismatch:\n"
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<< print(LISLR, *MRI);
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reportMismatch(LISLR, TrackedLR, MRI->getTargetRegisterInfo());
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return false;
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}
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auto LISPressure = getRegPressure(*MRI, LISLR);
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if (LISPressure != CurPressure) {
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dbgs() << "GCNUpwardRPTracker error: Pressure sets different\nTracked: "
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<< print(CurPressure) << "LIS rpt: " << print(LISPressure);
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return false;
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}
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return true;
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}
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Printable llvm::print(const GCNRPTracker::LiveRegSet &LiveRegs,
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const MachineRegisterInfo &MRI) {
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return Printable([&LiveRegs, &MRI](raw_ostream &OS) {
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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for (unsigned I = 0, E = MRI.getNumVirtRegs(); I != E; ++I) {
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Register Reg = Register::index2VirtReg(I);
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auto It = LiveRegs.find(Reg);
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if (It != LiveRegs.end() && It->second.any())
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OS << ' ' << printVRegOrUnit(Reg, TRI) << ':'
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<< PrintLaneMask(It->second);
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}
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OS << '\n';
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});
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}
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void GCNRegPressure::dump() const { dbgs() << print(*this); }
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static cl::opt<bool> UseDownwardTracker(
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"amdgpu-print-rp-downward",
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cl::desc("Use GCNDownwardRPTracker for GCNRegPressurePrinter pass"),
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cl::init(false), cl::Hidden);
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char llvm::GCNRegPressurePrinter::ID = 0;
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char &llvm::GCNRegPressurePrinterID = GCNRegPressurePrinter::ID;
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INITIALIZE_PASS(GCNRegPressurePrinter, "amdgpu-print-rp", "", true, true)
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bool GCNRegPressurePrinter::runOnMachineFunction(MachineFunction &MF) {
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const MachineRegisterInfo &MRI = MF.getRegInfo();
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const TargetRegisterInfo *TRI = MRI.getTargetRegisterInfo();
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const LiveIntervals &LIS = getAnalysis<LiveIntervals>();
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auto &OS = dbgs();
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// Leading spaces are important for YAML syntax.
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#define PFX " "
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OS << "---\nname: " << MF.getName() << "\nbody: |\n";
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auto printRP = [](const GCNRegPressure &RP) {
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return Printable([&RP](raw_ostream &OS) {
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OS << format(PFX " %-5d", RP.getSGPRNum())
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<< format(" %-5d", RP.getVGPRNum(false));
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});
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};
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auto ReportLISMismatchIfAny = [&](const GCNRPTracker::LiveRegSet &TrackedLR,
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const GCNRPTracker::LiveRegSet &LISLR) {
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if (LISLR != TrackedLR) {
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OS << PFX " mis LIS: " << llvm::print(LISLR, MRI)
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<< reportMismatch(LISLR, TrackedLR, TRI, PFX " ");
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}
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};
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// Register pressure before and at an instruction (in program order).
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SmallVector<std::pair<GCNRegPressure, GCNRegPressure>, 16> RP;
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for (auto &MBB : MF) {
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RP.clear();
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RP.reserve(MBB.size());
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OS << PFX;
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MBB.printName(OS);
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OS << ":\n";
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SlotIndex MBBStartSlot = LIS.getSlotIndexes()->getMBBStartIdx(&MBB);
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SlotIndex MBBEndSlot = LIS.getSlotIndexes()->getMBBEndIdx(&MBB);
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GCNRPTracker::LiveRegSet LiveIn, LiveOut;
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GCNRegPressure RPAtMBBEnd;
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if (UseDownwardTracker) {
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if (MBB.empty()) {
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LiveIn = LiveOut = getLiveRegs(MBBStartSlot, LIS, MRI);
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RPAtMBBEnd = getRegPressure(MRI, LiveIn);
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} else {
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GCNDownwardRPTracker RPT(LIS);
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RPT.reset(MBB.front());
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LiveIn = RPT.getLiveRegs();
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while (!RPT.advanceBeforeNext()) {
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GCNRegPressure RPBeforeMI = RPT.getPressure();
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RPT.advanceToNext();
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RP.emplace_back(RPBeforeMI, RPT.getPressure());
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}
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LiveOut = RPT.getLiveRegs();
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RPAtMBBEnd = RPT.getPressure();
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}
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} else {
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GCNUpwardRPTracker RPT(LIS);
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RPT.reset(MRI, MBBEndSlot);
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LiveOut = RPT.getLiveRegs();
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RPAtMBBEnd = RPT.getPressure();
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for (auto &MI : reverse(MBB)) {
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RPT.resetMaxPressure();
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RPT.recede(MI);
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if (!MI.isDebugInstr())
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RP.emplace_back(RPT.getPressure(), RPT.getMaxPressure());
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}
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LiveIn = RPT.getLiveRegs();
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}
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OS << PFX " Live-in: " << llvm::print(LiveIn, MRI);
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if (!UseDownwardTracker)
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ReportLISMismatchIfAny(LiveIn, getLiveRegs(MBBStartSlot, LIS, MRI));
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|
|
|
OS << PFX " SGPR VGPR\n";
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int I = 0;
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for (auto &MI : MBB) {
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|
if (!MI.isDebugInstr()) {
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|
auto &[RPBeforeInstr, RPAtInstr] =
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|
RP[UseDownwardTracker ? I : (RP.size() - 1 - I)];
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++I;
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OS << printRP(RPBeforeInstr) << '\n' << printRP(RPAtInstr) << " ";
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} else
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|
OS << PFX " ";
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|
MI.print(OS);
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|
}
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|
OS << printRP(RPAtMBBEnd) << '\n';
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|
|
|
OS << PFX " Live-out:" << llvm::print(LiveOut, MRI);
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|
if (UseDownwardTracker)
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|
ReportLISMismatchIfAny(LiveOut, getLiveRegs(MBBEndSlot, LIS, MRI));
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}
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OS << "...\n";
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return false;
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|
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#undef PFX
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} |