Konstantin Zhuravlyov f86e4b7266 [AMDGPU] Add f16 support (VI+) ...

Differential Revision: https://reviews.llvm.org/D25975

llvm-svn: 286753

2016-11-13 07:01:11 +00:00

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dpp_vi.txt

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ds_vi.txt

[AMDGPU][mc] Fix ds_min/max[_rtn]_f32 - extra source operand removed.

2016-10-21 14:49:22 +00:00

flat_vi.txt

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lit.local.cfg

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missing_op.txt

[AMDGPU] fix failure on printing of non-existing instruction operands.

2016-08-15 10:56:48 +00:00

mov.txt

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mubuf_vi.txt

[AMDGPU][mc] Add support for buffer_load_dwordx3, buffer_store_dwordx3.

2016-10-07 15:53:16 +00:00

nop.txt

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sdwa_vi.txt

[AMDGPU] Add f16 support (VI+)

2016-11-13 07:01:11 +00:00

smem_vi.txt

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smrd_vi.txt

[AMDGPU][MC][gfx8] Support 20-bit immediate offset in SMEM instructions.

2016-10-31 16:07:39 +00:00

sop1_vi.txt

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sop2_vi.txt

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sopc_vi.txt

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sopk_vi.txt

[AMDGPU][llvm-mc] s_getreg/setreg* - Support symbolic names of hardware registers.

2016-04-27 15:17:03 +00:00

sopp_vi.txt

[AMDGPU][llvm-mc] Add support for sendmsg(...) syntax.

2016-05-06 17:48:48 +00:00

trap_vi.txt

[AMDGPU][llvm-mc] Disassembler: support for TTMP/TBA/TMA registers.

2016-05-24 12:05:16 +00:00

vop1_vi.txt

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vop1.txt

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vop2_vi.txt

[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.

2016-06-06 15:23:43 +00:00

vop3_vi.txt

[AMDGPU][llvm-mc] v_cndmask_b32: src2 is mandatory; do not enforce VOP2 when src2 == VCC.

2016-06-06 15:23:43 +00:00

vopc_vi.txt

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