ad4a582fd9
Some targets (e.g. PPC and Hexagon) already did this. I think it's best to do this consistently so that frontend authors don't run into inconsistent results when they emit `naked` functions. For example, in Zig, we had to change our emit code to also set `frame-pointer=none` to get reliable results across targets. Note: I don't have commit access.
274 lines
9.8 KiB
C++
274 lines
9.8 KiB
C++
//===- XtensaFrameLowering.cpp - Xtensa Frame Information -----------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the Xtensa implementation of TargetFrameLowering class.
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//
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//===----------------------------------------------------------------------===//
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#include "XtensaFrameLowering.h"
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#include "XtensaInstrInfo.h"
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#include "XtensaSubtarget.h"
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#include "llvm/CodeGen/MachineFrameInfo.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineModuleInfo.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/CodeGen/RegisterScavenging.h"
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#include "llvm/IR/Function.h"
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using namespace llvm;
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XtensaFrameLowering::XtensaFrameLowering(const XtensaSubtarget &STI)
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: TargetFrameLowering(TargetFrameLowering::StackGrowsDown, Align(4), 0,
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Align(4)),
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TII(*STI.getInstrInfo()), TRI(STI.getRegisterInfo()) {}
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bool XtensaFrameLowering::hasFPImpl(const MachineFunction &MF) const {
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const MachineFrameInfo &MFI = MF.getFrameInfo();
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return MF.getTarget().Options.DisableFramePointerElim(MF) ||
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MFI.hasVarSizedObjects();
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}
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void XtensaFrameLowering::emitPrologue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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assert(&MBB == &MF.front() && "Shrink-wrapping not yet implemented");
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MachineFrameInfo &MFI = MF.getFrameInfo();
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MachineBasicBlock::iterator MBBI = MBB.begin();
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DebugLoc DL = MBBI != MBB.end() ? MBBI->getDebugLoc() : DebugLoc();
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MCRegister SP = Xtensa::SP;
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MCRegister FP = TRI->getFrameRegister(MF);
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const MCRegisterInfo *MRI = MF.getContext().getRegisterInfo();
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// First, compute final stack size.
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uint64_t StackSize = MFI.getStackSize();
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uint64_t PrevStackSize = StackSize;
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// Round up StackSize to 16*N
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StackSize += (16 - StackSize) & 0xf;
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// No need to allocate space on the stack.
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if (StackSize == 0 && !MFI.adjustsStack())
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return;
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// Adjust stack.
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TII.adjustStackPtr(SP, -StackSize, MBB, MBBI);
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// emit ".cfi_def_cfa_offset StackSize"
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unsigned CFIIndex =
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MF.addFrameInst(MCCFIInstruction::cfiDefCfaOffset(nullptr, StackSize));
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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if (!CSI.empty()) {
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// Find the instruction past the last instruction that saves a
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// callee-saved register to the stack. The callee-saved store
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// instructions are placed at the begin of basic block, so
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// iterate over instruction sequence and check that
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// save instructions are placed correctly.
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for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
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#ifndef NDEBUG
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const CalleeSavedInfo &Info = CSI[i];
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int FI = Info.getFrameIdx();
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int StoreFI = 0;
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// Checking that the instruction is exactly as expected
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bool IsStoreInst = false;
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if (MBBI->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
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Register DstReg = MBBI->getOperand(0).getReg();
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Register Reg = MBBI->getOperand(1).getReg();
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IsStoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
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} else {
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Register Reg = TII.isStoreToStackSlot(*MBBI, StoreFI);
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IsStoreInst = (Reg == Info.getReg()) && (StoreFI == FI);
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}
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assert(IsStoreInst &&
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"Unexpected callee-saved register store instruction");
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#endif
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++MBBI;
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}
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// Iterate over list of callee-saved registers and emit .cfi_offset
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// directives.
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for (const auto &I : CSI) {
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int64_t Offset = MFI.getObjectOffset(I.getFrameIdx());
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Register Reg = I.getReg();
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createOffset(
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nullptr, MRI->getDwarfRegNum(Reg, 1), Offset));
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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}
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// if framepointer enabled, set it to point to the stack pointer.
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if (hasFP(MF)) {
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// Insert instruction "move $fp, $sp" at this location.
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BuildMI(MBB, MBBI, DL, TII.get(Xtensa::OR), FP)
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.addReg(SP)
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.addReg(SP)
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.setMIFlag(MachineInstr::FrameSetup);
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// emit ".cfi_def_cfa_register $fp"
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unsigned CFIIndex = MF.addFrameInst(MCCFIInstruction::createDefCfaRegister(
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nullptr, MRI->getDwarfRegNum(FP, true)));
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BuildMI(MBB, MBBI, DL, TII.get(TargetOpcode::CFI_INSTRUCTION))
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.addCFIIndex(CFIIndex);
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}
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if (StackSize != PrevStackSize) {
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MFI.setStackSize(StackSize);
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for (int i = MFI.getObjectIndexBegin(); i < MFI.getObjectIndexEnd(); i++) {
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if (!MFI.isDeadObjectIndex(i)) {
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int64_t SPOffset = MFI.getObjectOffset(i);
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if (SPOffset < 0)
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MFI.setObjectOffset(i, SPOffset - StackSize + PrevStackSize);
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}
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}
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}
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}
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void XtensaFrameLowering::emitEpilogue(MachineFunction &MF,
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MachineBasicBlock &MBB) const {
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MachineBasicBlock::iterator MBBI = MBB.getLastNonDebugInstr();
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MachineFrameInfo &MFI = MF.getFrameInfo();
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DebugLoc DL = MBBI->getDebugLoc();
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MCRegister SP = Xtensa::SP;
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MCRegister FP = TRI->getFrameRegister(MF);
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// if framepointer enabled, restore the stack pointer.
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if (hasFP(MF)) {
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// We should place restore stack pointer instruction just before
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// sequence of instructions which restores callee-saved registers.
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// This sequence is placed at the end of the basic block,
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// so we should find first instruction of the sequence.
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MachineBasicBlock::iterator I = MBBI;
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const std::vector<CalleeSavedInfo> &CSI = MFI.getCalleeSavedInfo();
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// Find the first instruction at the end that restores a callee-saved
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// register.
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for (unsigned i = 0, e = CSI.size(); i < e; ++i) {
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--I;
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#ifndef NDEBUG
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const CalleeSavedInfo &Info = CSI[i];
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int FI = Info.getFrameIdx();
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int LoadFI = 0;
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// Checking that the instruction is exactly as expected
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bool IsRestoreInst = false;
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if (I->getOpcode() == TargetOpcode::COPY && Info.isSpilledToReg()) {
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Register Reg = I->getOperand(0).getReg();
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Register DstReg = I->getOperand(1).getReg();
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IsRestoreInst = (Info.getDstReg() == DstReg) && (Info.getReg() == Reg);
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} else {
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Register Reg = TII.isLoadFromStackSlot(*I, LoadFI);
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IsRestoreInst = (Info.getReg() == Reg) && (LoadFI == FI);
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}
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assert(IsRestoreInst &&
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"Unexpected callee-saved register restore instruction");
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#endif
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}
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BuildMI(MBB, I, DL, TII.get(Xtensa::OR), SP).addReg(FP).addReg(FP);
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}
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// Get the number of bytes from FrameInfo
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uint64_t StackSize = MFI.getStackSize();
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if (!StackSize)
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return;
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// Adjust stack.
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TII.adjustStackPtr(SP, StackSize, MBB, MBBI);
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}
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bool XtensaFrameLowering::spillCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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ArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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MachineFunction *MF = MBB.getParent();
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MachineBasicBlock &EntryBlock = *(MF->begin());
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for (unsigned i = 0, e = CSI.size(); i != e; ++i) {
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// Add the callee-saved register as live-in. Do not add if the register is
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// A0 and return address is taken, because it will be implemented in
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// method XtensaTargetLowering::LowerRETURNADDR.
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// It's killed at the spill, unless the register is RA and return address
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// is taken.
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Register Reg = CSI[i].getReg();
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bool IsA0AndRetAddrIsTaken =
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(Reg == Xtensa::A0) && MF->getFrameInfo().isReturnAddressTaken();
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if (!IsA0AndRetAddrIsTaken)
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EntryBlock.addLiveIn(Reg);
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// Insert the spill to the stack frame.
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bool IsKill = !IsA0AndRetAddrIsTaken;
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const TargetRegisterClass *RC = TRI->getMinimalPhysRegClass(Reg);
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TII.storeRegToStackSlot(EntryBlock, MI, Reg, IsKill, CSI[i].getFrameIdx(),
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RC, TRI, Register());
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}
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return true;
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}
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bool XtensaFrameLowering::restoreCalleeSavedRegisters(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MI,
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MutableArrayRef<CalleeSavedInfo> CSI, const TargetRegisterInfo *TRI) const {
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return TargetFrameLowering::restoreCalleeSavedRegisters(MBB, MI, CSI, TRI);
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}
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// Eliminate ADJCALLSTACKDOWN, ADJCALLSTACKUP pseudo instructions
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MachineBasicBlock::iterator XtensaFrameLowering::eliminateCallFramePseudoInstr(
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MachineFunction &MF, MachineBasicBlock &MBB,
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MachineBasicBlock::iterator I) const {
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const XtensaInstrInfo &TII =
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*static_cast<const XtensaInstrInfo *>(MF.getSubtarget().getInstrInfo());
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if (!hasReservedCallFrame(MF)) {
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int64_t Amount = I->getOperand(0).getImm();
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if (I->getOpcode() == Xtensa::ADJCALLSTACKDOWN)
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Amount = -Amount;
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TII.adjustStackPtr(Xtensa::SP, Amount, MBB, I);
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}
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return MBB.erase(I);
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}
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void XtensaFrameLowering::determineCalleeSaves(MachineFunction &MF,
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BitVector &SavedRegs,
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RegScavenger *RS) const {
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unsigned FP = TRI->getFrameRegister(MF);
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TargetFrameLowering::determineCalleeSaves(MF, SavedRegs, RS);
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// Mark $fp as used if function has dedicated frame pointer.
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if (hasFP(MF))
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SavedRegs.set(FP);
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}
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void XtensaFrameLowering::processFunctionBeforeFrameFinalized(
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MachineFunction &MF, RegScavenger *RS) const {
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// Set scavenging frame index if necessary.
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MachineFrameInfo &MFI = MF.getFrameInfo();
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uint64_t MaxSPOffset = MFI.estimateStackSize(MF);
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if (isInt<12>(MaxSPOffset))
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return;
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const TargetRegisterClass &RC = Xtensa::ARRegClass;
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unsigned Size = TRI->getSpillSize(RC);
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Align Alignment = TRI->getSpillAlign(RC);
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int FI = MF.getFrameInfo().CreateStackObject(Size, Alignment, false);
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RS->addScavengingFrameIndex(FI);
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}
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