b356aa3e2d
This is still relying on the manual code for splitting 64-bit constants, and handling pointers. We were missing some of the tablegen patterns for all immediate types, so this has some side effect DAG path improvements. This also reduces the diff in the 2 selector outputs.
40 lines
1.8 KiB
LLVM
40 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel -mtriple=amdgcn-- -verify-machineinstrs -mem-intrinsic-expand-size=3 %s -o - | FileCheck -check-prefix=LOOP %s
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; RUN: llc -global-isel -mtriple=amdgcn-- -verify-machineinstrs -mem-intrinsic-expand-size=5 %s -o - | FileCheck -check-prefix=UNROLL %s
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declare void @llvm.memset.p1.i32(ptr addrspace(1), i8, i32, i1)
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define amdgpu_cs void @memset_p1i8(ptr addrspace(1) %dst, i8 %val) {
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; LOOP-LABEL: memset_p1i8:
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; LOOP: ; %bb.0: ; %loadstoreloop.preheader
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; LOOP-NEXT: s_mov_b64 s[0:1], 0
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; LOOP-NEXT: s_mov_b32 s2, 0
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; LOOP-NEXT: s_mov_b32 s3, 0xf000
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; LOOP-NEXT: v_mov_b32_e32 v4, s1
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; LOOP-NEXT: v_mov_b32_e32 v3, s0
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; LOOP-NEXT: .LBB0_1: ; %loadstoreloop
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; LOOP-NEXT: ; =>This Inner Loop Header: Depth=1
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; LOOP-NEXT: v_add_i32_e32 v5, vcc, v0, v3
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; LOOP-NEXT: v_addc_u32_e32 v6, vcc, v1, v4, vcc
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; LOOP-NEXT: v_add_i32_e32 v3, vcc, 1, v3
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; LOOP-NEXT: v_addc_u32_e32 v4, vcc, 0, v4, vcc
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; LOOP-NEXT: v_cmp_gt_u32_e32 vcc, 4, v3
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; LOOP-NEXT: buffer_store_byte v2, v[5:6], s[0:3], 0 addr64
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; LOOP-NEXT: s_cbranch_vccnz .LBB0_1
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; LOOP-NEXT: ; %bb.2: ; %split
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; LOOP-NEXT: s_endpgm
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;
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; UNROLL-LABEL: memset_p1i8:
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; UNROLL: ; %bb.0:
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; UNROLL-NEXT: s_mov_b32 s2, 0
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; UNROLL-NEXT: s_mov_b32 s3, 0xf000
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; UNROLL-NEXT: s_mov_b64 s[0:1], 0
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; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64
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; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:1
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; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:2
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; UNROLL-NEXT: buffer_store_byte v2, v[0:1], s[0:3], 0 addr64 offset:3
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; UNROLL-NEXT: s_endpgm
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call void @llvm.memset.p1.i32(ptr addrspace(1) %dst, i8 %val, i32 4, i1 false)
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ret void
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}
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