caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
a78861fc55d18046989ff4d624a037e9181da170
clang-p2996/llvm/test/CodeGen/AMDGPU/GlobalISel
History
Fabian Ritter a4fd3dba6e [AMDGPU] Use wider loop lowering type for LowerMemIntrinsics (#112332) 
When llvm.memcpy or llvm.memmove intrinsics are lowered as a loop in
LowerMemIntrinsics.cpp, the loop consists of a single load/store pair
per iteration. We can improve performance in some cases by emitting
multiple load/store pairs per iteration. This patch achieves that by
increasing the width of the loop lowering type in the GCN target and
letting legalization split the resulting too-wide access pairs into
multiple legal access pairs.

This change only affects lowered memcpys and memmoves with large (>=
1024 bytes) constant lengths. Smaller constant lengths are handled by
ISel directly; non-constant lengths would be slowed down by this change
if the dynamic length was smaller or slightly larger than what an
unrolled iteration copies.

The chosen default unroll factor is the result of microbenchmarks on
gfx1030. This change leads to speedups of 15-38% for global memory and
1.9-5.8x for scratch in these microbenchmarks.

Part of SWDEV-455845.
2024-10-28 09:04:19 +01:00
..
add_shl.ll
…
add.v2i16.ll
AMDGPU: Materialize bitwise not of inline immediates (#95960)
2024-06-22 00:40:59 +02:00
add.vni16.ll
…
addo.ll
…
addsubu64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
amdgpu-irtranslator.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
amdgpu-prelegalizer-combiner-crash.mir
…
andn2.ll
…
artifact-combiner-anyext.mir
…
artifact-combiner-asserts.ll
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
artifact-combiner-build-vector.mir
…
artifact-combiner-concat-vectors.mir
…
artifact-combiner-cse-leaves-dead-cast.mir
…
artifact-combiner-extract.mir
…
artifact-combiner-sext.mir
…
artifact-combiner-trunc.mir
…
artifact-combiner-unmerge-values.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
artifact-combiner-zext.mir
…
ashr.ll
[GlobalIsel] Push cast through select. (#100539)
2024-07-25 19:21:28 +02:00
assert-align.ll
Reapply "[CodeGen]Allow targets to use target specific COPY instructions for live range splitting"
2023-07-31 20:15:45 -04:00
atomic_load_local.ll
AMDGPU: Bulk update all GlobalISel tests to use opaque pointers
2022-11-28 11:51:36 -05:00
atomic_optimizations_mul_one.ll
[AMDGPU] Extend readlane, writelane and readfirstlane intrinsic lowering for generic types (#89217)
2024-06-25 14:35:19 +05:30
atomic_store_local.ll
…
atomicrmw_fmax.ll
[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)
2024-10-07 07:35:31 +02:00
atomicrmw_fmin.ll
[AMDGPU] Only emit SCOPE_SYS global_wb (#110636)
2024-10-07 07:35:31 +02:00
atomicrmw_udec_wrap.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
atomicrmw_uinc_wrap.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
bitcast_38_i16.ll
…
bool-legalization.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
br-constant-invalid-sgpr-copy.ll
…
bswap.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
buffer-atomic-fadd.f32-no-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.f32-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.f64.ll
…
buffer-atomic-fadd.v2f16-no-rtn.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
buffer-atomic-fadd.v2f16-rtn.ll
…
buffer-schedule.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
bug-legalization-artifact-combiner-dead-def.ll
…
bug-legalization-artifact-combiner-dead-def.mir
…
call-outgoing-stack-args.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
clamp-fmed3-const-combine.ll
…
clamp-minmax-const-combine.ll
…
combine-add-nullptr.mir
…
combine-add-to-ptradd.mir
…
combine-amdgpu-cvt-f32-ubyte.mir
…
combine-ashr-narrow.mir
…
combine-ext-legalizer.mir
…
combine-extract-vector-load.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
combine-fabs-fneg.mir
…
combine-fcanonicalize.mir
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
combine-fdiv-sqrt-to-rsq.mir
[AMDGPU][GlobalISel] Add fdiv / sqrt to rsq combine (#78673)
2024-02-22 09:47:36 +01:00
combine-fma-add-ext-fma.ll
AMDGPU/GlobalISel: Fix isExtractHiElt when selecting fma_mix (#102130)
2024-08-07 12:13:39 +02:00
combine-fma-add-ext-mul.ll
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
combine-fma-add-fma-mul.ll
…
combine-fma-add-mul-post-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul-pre-legalize.mir
[AArch64][AMDGPU][GlobalISel] Remove vector handling from unmerge_dead_to_trunc (#82224)
2024-02-20 10:54:44 +00:00
combine-fma-add-mul.ll
…
combine-fma-sub-ext-mul.ll
…
combine-fma-sub-ext-neg-mul.ll
…
combine-fma-sub-mul.ll
…
combine-fma-sub-neg-mul.ll
…
combine-fma-unmerge-values.mir
…
combine-fold-binop-into-select.mir
…
combine-foldable-fneg.mir
…
combine-fpneg-one-fneg.mir
[AMDGPU,test] Change llc -march= to -mtriple=
2024-03-07 19:09:18 -08:00
combine-fsh.mir
…
combine-fsub-fneg.mir
…
combine-itofp.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combine-lshr-narrow.mir
…
combine-or-redundant.mir
…
combine-redundant-and.mir
…
combine-redundant-neg.mir
…
combine-rot.mir
…
combine-rsq.ll
…
combine-rsq.mir
…
combine-sext-inreg.mir
…
combine-shift-imm-chain-illegal-types.mir
…
combine-shift-imm-chain-shlsat.mir
…
combine-shift-imm-chain.ll
…
combine-shift-of-shifted-logic-shlsat.mir
…
combine-shift-of-shifted-logic.ll
…
combine-shl-from-extend-narrow.postlegal.mir
…
combine-shl-from-extend-narrow.prelegal.mir
…
combine-shl-narrow.mir
…
combine-short-clamp.ll
…
combine-trunc-shift.mir
…
combine-urem-pow-2.mir
…
combine-zext-trunc.mir
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
combiner-crash.ll
…
compute-num-sign-bits-med3.mir
…
constant-bus-restriction.ll
…
crash-stack-address-O0.ll
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
2024-08-01 09:42:04 +04:00
cvt_f32_ubyte.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
dereferenceable-declaration.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
divergence-divergent-i1-phis-no-lane-mask-merging.ll
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
2024-09-23 13:20:21 +04:00
divergence-divergent-i1-phis-no-lane-mask-merging.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
divergence-divergent-i1-used-outside-loop.ll
AMDGPU: Fix implicit vcc def to vcc_lo on wave32 targets (#109514)
2024-09-23 13:20:21 +04:00
divergence-divergent-i1-used-outside-loop.mir
[AMDGPU]: Add implicit-def to the BB prolog (#112872)
2024-10-21 13:21:16 +05:30
divergence-structurizer.ll
AMDGPU/GlobalISel: lane masks merging (#73337)
2024-02-29 13:57:59 +01:00
divergence-structurizer.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
divergence-temporal-divergent-i1.ll
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
divergence-temporal-divergent-i1.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
divergence-temporal-divergent-reg.ll
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
divergence-temporal-divergent-reg.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
divergent-control-flow.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
dropped_debug_info_assert.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
dummy-target.ll
[AMDGPU] Remove function with incompatible features
2023-02-21 10:42:39 +01:00
dynamic-alloca-divergent.ll
…
dynamic-alloca-uniform.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
extractelement-stack-lower.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.i8.ll
[GISel] Combine (Scalarize) vector load followed by an element extract.
2023-12-06 11:23:23 +05:30
extractelement.i16.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.i128.ll
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
extractelement.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
fdiv.f16.ll
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
fdiv.f32.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fdiv.f64.ll
[GlobalIsel] Canonicalize G_ICMP (#108755)
2024-09-16 19:25:34 +02:00
flat-atomic-fadd.f32.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
flat-atomic-fadd.f64.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
flat-atomic-fadd.v2f16.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
flat-scratch-init.gfx.ll
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
2024-08-01 09:42:04 +04:00
flat-scratch-init.ll
[Attributor] Skip AS specialization for volatile memory instructions (#107250)
2024-09-06 11:00:30 -04:00
flat-scratch.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
floor.f64.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
fma.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
fmamix-constant-bus-violation.ll
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
fmamix-constant-bus-violation.mir
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
fmax_legacy.ll
…
fmed3-min-max-const-combine.ll
…
fmin_legacy.ll
…
fmul.v2f16.ll
…
fp64-atomics-gfx90a.ll
AMDGPU: Remove flat/global fmin/fmax intrinsics (#105642)
2024-10-09 09:27:28 +04:00
fp-atomics-gfx940.ll
AMDGPU: Remove global/flat atomic fadd intrinics (#97051)
2024-08-22 23:27:33 +04:00
fpow.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
frem.ll
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
fshl.ll
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
fshr.ll
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
function-returns.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
function-returns.v2i65.ll
[GlobalISel] Allow more illegal vector types in params/returns. (#95514)
2024-06-18 13:20:49 +01:00
global-atomic-fadd.f32-no-rtn.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
global-atomic-fadd.f32-rtn.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
global-atomic-fadd.f64.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
global-atomic-fadd.v2f16-no-rtn.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
global-atomic-fadd.v2f16-rtn.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
global-value.illegal.ll
AMDGPU: Bulk update all GlobalISel tests to use opaque pointers
2022-11-28 11:51:36 -05:00
global-value.ll
[AMDGPU] Tweak handling of GlobalAddress operands in SI_PC_ADD_REL_OFFSET (#70960)
2023-11-01 19:48:30 +00:00
hip.extern.shared.array.ll
AMDGPU: Bulk update all GlobalISel tests to use opaque pointers
2022-11-28 11:51:36 -05:00
i1-copy.ll
…
image-waterfall-loop-O0.ll
[AMDGPU]: Add implicit-def to the BB prolog (#112872)
2024-10-21 13:21:16 +05:30
implicit-kernarg-backend-usage-global-isel.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
inline-asm-mismatched-size.ll
[AMDGPU] Check vector sizes for physical register constraints in inline asm (#109955)
2024-10-01 10:29:35 +02:00
inline-asm.ll
Reapply "RegAllocFast: Rewrite and improve"
2020-09-30 10:35:25 -04:00
insertelement-stack-lower.ll
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
2024-08-01 09:42:04 +04:00
insertelement.i8.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
insertelement.i16.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
insertelement.large.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
insertelement.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
inst-select-abs.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-add.mir
…
inst-select-add.s16.mir
[AMDGPU][True16][MC] VOP3 profile in True16 format (#109031)
2024-10-16 10:27:44 -04:00
inst-select-amdgcn.class.mir
…
inst-select-amdgcn.class.s16.mir
…
inst-select-amdgcn.cos.mir
…
inst-select-amdgcn.cos.s16.mir
…
inst-select-amdgcn.cvt.pk.i16.mir
…
inst-select-amdgcn.cvt.pk.u16.mir
…
inst-select-amdgcn.cvt.pknorm.i16.mir
…
inst-select-amdgcn.cvt.pknorm.u16.mir
…
inst-select-amdgcn.cvt.pkrtz.mir
…
inst-select-amdgcn.ds.swizzle.mir
…
inst-select-amdgcn.exp.compr.mir
…
inst-select-amdgcn.exp.mir
…
inst-select-amdgcn.fcmp.constants.w32.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-amdgcn.fcmp.constants.w64.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-amdgcn.fmad.ftz.mir
…
inst-select-amdgcn.fmed3.mir
…
inst-select-amdgcn.fmed3.s16.mir
…
inst-select-amdgcn.fract.mir
…
inst-select-amdgcn.fract.s16.mir
…
inst-select-amdgcn.groupstaticsize.mir
…
inst-select-amdgcn.mbcnt.lo.mir
…
inst-select-amdgcn.mul.u24.mir
…
inst-select-amdgcn.mulhi.i24.mir
…
inst-select-amdgcn.mulhi.u24.mir
…
inst-select-amdgcn.rcp.legacy.mir
…
inst-select-amdgcn.rcp.mir
…
inst-select-amdgcn.rcp.s16.mir
…
inst-select-amdgcn.readfirstlane.mir
…
inst-select-amdgcn.reloc.constant.mir
…
inst-select-amdgcn.rsq.clamp.mir
…
inst-select-amdgcn.rsq.legacy.mir
…
inst-select-amdgcn.rsq.mir
…
inst-select-amdgcn.rsq.s16.mir
…
inst-select-amdgcn.s.barrier.mir
…
inst-select-amdgcn.s.sendmsg.mir
…
inst-select-amdgcn.sffbh.mir
…
inst-select-amdgcn.sin.mir
…
inst-select-amdgcn.sin.s16.mir
…
inst-select-amdgpu-atomic-cmpxchg-flat.mir
…
inst-select-amdgpu-atomic-cmpxchg-global.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-amdgpu-ffbh-u32.mir
…
inst-select-amdgpu-ffbl-b32.mir
…
inst-select-amdgpu-wave-address.mir
…
inst-select-and.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-anyext.mir
…
inst-select-ashr.mir
…
inst-select-ashr.s16.mir
[AMDGPU][True16][MC] Support VOP3 only instructions with true16 and fake16 (#109891)
2024-10-01 09:25:36 -04:00
inst-select-ashr.v2s16.mir
…
inst-select-atomic-cmpxchg-local.mir
…
inst-select-atomic-cmpxchg-region.mir
…
inst-select-atomicrmw-add-flat.mir
…
inst-select-atomicrmw-add-global.mir
…
inst-select-atomicrmw-fadd-local.mir
…
inst-select-atomicrmw-fadd-region.mir
…
inst-select-atomicrmw-xchg-local.mir
…
inst-select-atomicrmw-xchg-region.mir
…
inst-select-bitcast.mir
…
inst-select-bitreverse.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-br.mir
…
inst-select-brcond.mir
…
inst-select-bswap.mir
…
inst-select-build-vector-trunc.v2s16.mir
…
inst-select-build-vector.mir
[AMDGPU] Regenerate MIR checks. NFC.
2022-06-27 12:15:29 +01:00
inst-select-concat-vectors.mir
…
inst-select-constant.mir
AMDGPU/GlobalISel: Select all constants in tablegen (#100788)
2024-07-30 18:31:18 +04:00
inst-select-copy.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-ctlz-zero-undef.mir
…
inst-select-ctpop.mir
…
inst-select-cttz-zero-undef.mir
…
inst-select-extract-vector-elt.mir
…
inst-select-extract.mir
…
inst-select-fabs.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-fadd.s16.mir
…
inst-select-fadd.s32.mir
…
inst-select-fadd.s64.mir
…
inst-select-fcanonicalize.mir
…
inst-select-fceil.mir
…
inst-select-fceil.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fcmp.mir
…
inst-select-fcmp.s16.mir
[AMDGPU][True16][MC] added VOPC realtrue/faketrue flag and fake16 instructions (#104739)
2024-08-21 17:47:36 +03:00
inst-select-fconstant.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-fexp2.mir
…
inst-select-ffloor.s16.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-ffloor.s32.mir
…
inst-select-ffloor.s64.mir
…
inst-select-fma.s32.mir
…
inst-select-fmad.s32.mir
…
inst-select-fmaxnum-ieee.mir
…
inst-select-fmaxnum-ieee.s16.mir
…
inst-select-fmaxnum-ieee.v2s16.mir
…
inst-select-fmaxnum.mir
…
inst-select-fmaxnum.s16.mir
…
inst-select-fmaxnum.v2s16.mir
…
inst-select-fminnum-ieee.mir
…
inst-select-fminnum-ieee.s16.mir
…
inst-select-fminnum-ieee.v2s16.mir
…
inst-select-fminnum.mir
…
inst-select-fminnum.s16.mir
…
inst-select-fminnum.v2s16.mir
…
inst-select-fmul.mir
…
inst-select-fmul.v2s16.mir
…
inst-select-fneg.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-fptosi.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fptoui.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-fract.f64.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-frame-index.mir
…
inst-select-freeze.mir
…
inst-select-fshr.mir
…
inst-select-i1-copy.mir
…
inst-select-icmp.mir
…
inst-select-icmp.s16.mir
…
inst-select-icmp.s64.mir
…
inst-select-implicit-def.mir
[AMDGPU] Regenerate MIR checks. NFC.
2022-06-27 12:15:29 +01:00
inst-select-insert-vector-elt.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-insert.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-intrinsic-trunc.mir
…
inst-select-intrinsic-trunc.s16.mir
…
inst-select-inttoptr.mir
…
inst-select-load-atomic-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-atomic-global.mir
…
inst-select-load-atomic-local.mir
…
inst-select-load-constant.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-load-flat.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-load-global-saddr.mir
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
inst-select-load-global.mir
…
inst-select-load-global.s96.mir
[AMDGPU] Regenerate checks in inst-select-load-global.s96.mir
2024-05-30 14:02:15 +01:00
inst-select-load-local-128.mir
…
inst-select-load-local.mir
Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v2 (#111708)"
2024-10-10 13:37:44 +02:00
inst-select-load-private.mir
…
inst-select-load-smrd.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-lshr.mir
…
inst-select-lshr.s16.mir
[AMDGPU][True16][MC] Support VOP3 only instructions with true16 and fake16 (#109891)
2024-10-01 09:25:36 -04:00
inst-select-lshr.v2s16.mir
…
inst-select-mad_64_32.mir
…
inst-select-merge-values.mir
…
inst-select-mul.mir
…
inst-select-or.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-pattern-add3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-and-or.mir
…
inst-select-pattern-or3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-smed3.mir
…
inst-select-pattern-smed3.s16.mir
[AMDGPU][True16][MC] Support VOP3 only instructions with true16 and fake16 (#109891)
2024-10-01 09:25:36 -04:00
inst-select-pattern-umed3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-pattern-umed3.s16.mir
[AMDGPU][True16][MC] Support VOP3 only instructions with true16 and fake16 (#109891)
2024-10-01 09:25:36 -04:00
inst-select-pattern-xor3.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-phi.mir
AMDGPU\GlobalISel: remove amdgpu-global-isel-risky-select flag (#83426)
2024-02-29 15:38:54 +01:00
inst-select-pseudo-scalar-transcendental.mir
…
inst-select-ptr-add.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-ptrmask.mir
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
inst-select-ptrtoint.mir
…
inst-select-returnaddress.mir
…
inst-select-sbfx.mir
…
inst-select-scalar-float-sop1.mir
…
inst-select-scalar-float-sop2.mir
…
inst-select-scalar-float-sopc.mir
…
inst-select-scalar-packed.xfail.mir
…
inst-select-select.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-sext-inreg.mir
…
inst-select-sext.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-sextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
inst-select-shl.mir
…
inst-select-shl.s16.mir
[AMDGPU][True16][MC] Support VOP3 only instructions with true16 and fake16 (#109891)
2024-10-01 09:25:36 -04:00
inst-select-shl.v2s16.mir
…
inst-select-sitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-smax.mir
…
inst-select-smin.mir
…
inst-select-smulh.mir
…
inst-select-stacksave-stackrestore.invalid.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-stacksave-stackrestore.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-store-atomic-flat.mir
…
inst-select-store-atomic-local.mir
…
inst-select-store-flat.mir
…
inst-select-store-global.mir
…
inst-select-store-global.s96.mir
…
inst-select-store-local.mir
…
inst-select-store-private.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-sub.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-trunc.mir
…
inst-select-trunc.v2s16.mir
…
inst-select-uadde.gfx10.mir
…
inst-select-uadde.mir
…
inst-select-uaddo.mir
…
inst-select-ubfx.mir
…
inst-select-uitofp.mir
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
inst-select-umax.mir
…
inst-select-umin.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
inst-select-umulh.mir
…
inst-select-unmerge-values.mir
[AMDGPU] Fix failing test after #109958 (#109964)
2024-09-25 15:02:23 +02:00
inst-select-usube.gfx10.mir
…
inst-select-usube.mir
…
inst-select-usubo.mir
…
inst-select-xor.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
inst-select-zext.mir
[GlobalISel][TableGen] Take first result for multi-output instructions (#81130)
2024-03-02 20:10:02 +01:00
inst-select-zextload-local.mir
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
irtranslate-bf16.ll
…
irtranslator-amdgcn-cs-chain.ll
…
irtranslator-amdgcn-sendmsg.ll
…
irtranslator-amdgpu_kernel-system-sgprs.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
irtranslator-amdgpu_kernel.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
irtranslator-amdgpu_ps.ll
…
irtranslator-amdgpu_vs.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
irtranslator-assert-align.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-atomicrmw.ll
AMDGPU: Legalize atomicrmw fadd for v2f16/v2bf16 for local memory (#95393)
2024-06-15 09:55:04 +02:00
irtranslator-call-abi-attribute-hints.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-implicit-args.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-call-non-fixed.ll
Revert "Update amdgpu_gfx functions to use s0-s3 for inreg SGPR arguments on targets using scratch instructions for stack #78226" (#86273)
2024-03-26 11:01:08 +01:00
irtranslator-call-return-values.ll
[GlobalIsel] Import GEP flags (#93850)
2024-06-14 20:56:43 +02:00
irtranslator-call-sret.ll
[GlobalIsel] Import GEP flags (#93850)
2024-06-14 20:56:43 +02:00
irtranslator-call.ll
[GlobalIsel] Import GEP flags (#93850)
2024-06-14 20:56:43 +02:00
irtranslator-constant-fold-vector-op.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-constantexpr.ll
[IR] Remove FP cast constant expressions (#71408)
2023-11-07 09:34:16 +01:00
irtranslator-constrained-fp.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-fast-math-flags.ll
…
irtranslator-fence.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
irtranslator-fixed-function-abi-vgpr-args.ll
…
irtranslator-function-args.ll
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
irtranslator-function-args.v2i65.ll
[GlobalISel] Allow more illegal vector types in params/returns. (#95514)
2024-06-18 13:20:49 +01:00
irtranslator-getelementptr.ll
AMDGPU: Bulk update all GlobalISel tests to use opaque pointers
2022-11-28 11:51:36 -05:00
irtranslator-indirect-call.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-inline-asm.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-invariant.ll
…
irtranslator-memory-intrinsics.ll
…
irtranslator-metadata.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
irtranslator-non-integral-address-spaces-vectors.ll
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
irtranslator-non-integral-address-spaces.ll
[AMDGPU] Add IR-level pass to rewrite away address space 7 (#77952)
2024-03-06 09:49:58 -06:00
irtranslator-prefetch.ll
[GlobalISel] Add G_PREFETCH (#74863)
2023-12-11 11:06:50 +00:00
irtranslator-ptrmask.ll
…
irtranslator-readnone-intrinsic-callsite.ll
…
irtranslator-sat.ll
…
irtranslator-sibling-call.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
irtranslator-struct-return-intrinsics.ll
…
irtranslator-tail-call.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
irtranslator-zext-vec-index.ll
…
is-safe-to-sink-bug.ll
AMDGPU: fix isSafeToSink expecting exactly one predecessor (#89224)
2024-05-10 13:02:05 +02:00
lds-global-value.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
lds-misaligned-bug.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
lds-relocs.ll
…
lds-zero-initializer.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
legalize-abs.mir
…
legalize-add.mir
…
legalize-addrspacecast.mir
[AMDGPU][GlobalISel] Save a copy in one case of addrspacecast (#104789)
2024-08-19 18:22:29 +01:00
legalize-amdgcn.if-invalid.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
legalize-amdgcn.if.xfail.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
legalize-amdgcn.rsq.clamp.mir
…
legalize-amdgcn.wavefrontsize.mir
…
legalize-amdgcn.workitem.id.mir
…
legalize-and.mir
…
legalize-anyext.mir
…
legalize-ashr.mir
…
legalize-atomic-cmpxchg-with-success.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-atomic-cmpxchg.mir
…
legalize-atomicrmw-add.mir
…
legalize-atomicrmw-and.mir
…
legalize-atomicrmw-fadd-global.mir
…
legalize-atomicrmw-fadd-local.mir
…
legalize-atomicrmw-max.mir
…
legalize-atomicrmw-min.mir
…
legalize-atomicrmw-nand.mir
…
legalize-atomicrmw-or.mir
…
legalize-atomicrmw-sub.mir
…
legalize-atomicrmw-umax.mir
…
legalize-atomicrmw-umin.mir
…
legalize-atomicrmw-xchg-flat.mir
…
legalize-atomicrmw-xchg.mir
…
legalize-atomicrmw-xor.mir
…
legalize-bitcast.mir
…
legalize-bitreverse.mir
…
legalize-block-addr.mir
…
legalize-brcond.mir
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
legalize-bswap.mir
…
legalize-build-vector-splat.mir
…
legalize-build-vector-trunc.mir
…
legalize-build-vector.mir
…
legalize-build-vector.s16.mir
…
legalize-concat-vectors.mir
…
legalize-constant.mir
…
legalize-ctlz-zero-undef.mir
[LegalizeDAG] Optimize CodeGen for ISD::CTLZ_ZERO_UNDEF (#83039)
2024-07-08 14:01:32 +01:00
legalize-ctlz.mir
…
legalize-ctpop.mir
…
legalize-cttz-zero-undef.mir
…
legalize-cttz.mir
…
legalize-extract-vector-elt.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-extract.mir
…
legalize-extractelement-crash.mir
[AArch64][GlobalISel] Legalize Insert vector element (#81453)
2024-04-08 08:44:13 +01:00
legalize-fabs.mir
…
legalize-fadd.mir
…
legalize-fcanonicalize.mir
…
legalize-fceil.mir
…
legalize-fcmp-s32.mir
…
legalize-fcmp.mir
…
legalize-fconstant.mir
…
legalize-fcopysign.mir
DAG/GlobalISel: Set disjoint for or in copysign lowering (#97057)
2024-06-28 23:03:39 +02:00
legalize-fcos.mir
…
legalize-fdiv.mir
[AMDGPU] Adopt new lowering sequence for fdiv16 (#109295)
2024-10-08 09:49:20 -04:00
legalize-fexp2.mir
…
legalize-fexp.mir
…
legalize-ffloor.mir
…
legalize-flog2.mir
…
legalize-flog10.mir
…
legalize-flog.mir
…
legalize-fma.mir
…
legalize-fmad.s16.mir
…
legalize-fmad.s32.mir
…
legalize-fmad.s64.mir
…
legalize-fmaxnum.mir
…
legalize-fminnum.mir
…
legalize-fmul.mir
…
legalize-fneg.mir
…
legalize-fpext.mir
…
legalize-fpow.mir
…
legalize-fpowi.mir
…
legalize-fptosi.mir
…
legalize-fptoui.mir
…
legalize-fptrunc.mir
…
legalize-freeze.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-fshl.mir
…
legalize-fshr.mir
…
legalize-fsin.mir
…
legalize-fsqrt.mir
…
legalize-fsub.mir
…
legalize-icmp.mir
…
legalize-implicit-def-s1025.mir
…
legalize-implicit-def.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert-vector-elt.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-insert.mir
…
legalize-intrinsic-amdgcn-fdiv-fast.mir
…
legalize-intrinsic-round.mir
DAG/GlobalISel: Set disjoint for or in copysign lowering (#97057)
2024-06-28 23:03:39 +02:00
legalize-intrinsic-trunc.mir
…
legalize-inttoptr.mir
…
legalize-jump-table.mir
…
legalize-llvm.amdgcn.image.atomic.dim.a16.ll
…
legalize-llvm.amdgcn.image.dim.a16.ll
…
legalize-llvm.amdgcn.image.load.2d.d16.ll
…
legalize-llvm.amdgcn.image.load.2d.ll
…
legalize-llvm.amdgcn.image.load.2darraymsaa.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.load.3d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.a16.ll
…
legalize-llvm.amdgcn.image.sample.d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.a16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.sample.g16.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
legalize-llvm.amdgcn.image.store.2d.d16.ll
…
legalize-llvm.amdgcn.s.buffer.load.mir
[AMDGPU][GISel] Use datalayout alignment for buffer-load legalization (#95578)
2024-06-15 18:19:52 +05:30
legalize-load-constant-32bit.mir
…
legalize-load-constant.mir
Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v2 (#111708)"
2024-10-10 13:37:44 +02:00
legalize-load-flat.mir
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
legalize-load-global.mir
Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v2 (#111708)"
2024-10-10 13:37:44 +02:00
legalize-load-local.mir
Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v2 (#111708)"
2024-10-10 13:37:44 +02:00
legalize-load-memory-metadata.mir
…
legalize-load-private.mir
[AMDGPU] Enable unaligned scratch accesses (#110219)
2024-10-11 08:50:49 +02:00
legalize-lshr.mir
…
legalize-memcpy.mir
…
legalize-memcpyinline.mir
…
legalize-memmove.mir
…
legalize-memset.mir
…
legalize-merge-values-build-vector.mir
…
legalize-merge-values.mir
…
legalize-mul.mir
…
legalize-or.mir
…
legalize-phi.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
legalize-ptr-add.mir
[GISel] Enforce G_PTR_ADD RHS type matching index size for addr space (#84352)
2024-03-09 09:07:22 +00:00
legalize-ptrmask.mir
…
legalize-ptrtoint.mir
…
legalize-rotl-rotr.mir
…
legalize-sadde.mir
…
legalize-saddo.mir
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
legalize-saddsat.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-sbfx.mir
…
legalize-sdiv.mir
…
legalize-select.mir
…
legalize-sext-inreg.mir
…
legalize-sext.mir
…
legalize-sextload-constant-32bit.mir
…
legalize-sextload-flat.mir
…
legalize-sextload-global.mir
…
legalize-sextload-local.mir
…
legalize-sextload-private.mir
…
legalize-shl.mir
…
legalize-shuffle-vector.mir
…
legalize-shuffle-vector.s16.mir
…
legalize-sitofp.mir
…
legalize-smax.mir
…
legalize-smin.mir
…
legalize-smulh.mir
…
legalize-smulo.mir
…
legalize-srem.mir
…
legalize-sshlsat.mir
…
legalize-ssube.mir
…
legalize-ssubo.mir
[GISel] LegalizationArtifactCombiner: Elide redundant G_SEXT_INREG (#93687)
2024-05-30 12:40:42 +03:00
legalize-ssubsat.mir
[GlobalISel] Fold G_ICMP if possible (#86357)
2024-03-29 15:59:50 -04:00
legalize-store-global.mir
Revert "Reapply "[AMDGPU][GlobalISel] Fix load/store of pointer vectors, buffer.*.pN (#110714)" v2 (#111708)"
2024-10-10 13:37:44 +02:00
legalize-store.mir
…
legalize-strict_fsub.mir
…
legalize-sub.mir
…
legalize-trap-gfx11.mir
[AMDGPU] Fix broken MIR generated by gfx11 simulated trap lowering (#91652)
2024-05-22 10:55:19 -04:00
legalize-trap.mir
[GlobalISel] Introduce G_TRAP, G_DEBUGTRAP, G_UBSANTRAP (#84941)
2024-03-23 13:12:44 +01:00
legalize-trunc.mir
[GlobalISel] Combine unmerge(unmerge()) if the result is legal. (#109606)
2024-09-25 07:04:09 +01:00
legalize-uadde.mir
…
legalize-uaddo.mir
…
legalize-uaddsat.mir
…
legalize-ubfx.mir
…
legalize-udiv.mir
…
legalize-uitofp.mir
…
legalize-umax.mir
…
legalize-umin.mir
…
legalize-umulh.mir
…
legalize-umulo.mir
…
legalize-unmerge-values.mir
…
legalize-urem.mir
…
legalize-ushlsat.mir
…
legalize-usube.mir
…
legalize-usubo.mir
…
legalize-usubsat.mir
…
legalize-vector-args-gfx7.mir
…
legalize-vector-args-gfx8-plus.mir
…
legalize-xor.mir
…
legalize-zext.mir
…
legalize-zextload-constant-32bit.mir
…
legalize-zextload-flat.mir
…
legalize-zextload-global.mir
…
legalize-zextload-local.mir
…
legalize-zextload-private.mir
…
llvm.abs.ll
[AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800)
2024-06-14 19:14:19 +02:00
llvm.amdgcn.ballot.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.ballot.i64.ll
AMDGPU/GlobalISel: Fix inst-selection of ballot (#109986)
2024-10-11 11:40:27 +02:00
llvm.amdgcn.dispatch.ptr.ll
[AMDGPU] Rename COV module flag to amdhsa_code_object_version (#79905)
2024-03-06 09:51:48 -05:00
llvm.amdgcn.div.fmas.ll
[AMDGPU] Promote uniform ops to I32 in DAGISel (#106383)
2024-09-19 09:00:21 +02:00
llvm.amdgcn.div.scale.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.end.cf.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.end.cf.i64.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.fdot2.ll
…
llvm.amdgcn.fmul.legacy.ll
…
llvm.amdgcn.global.atomic.csub.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.if.break.i32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.if.break.i64.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.image.atomic.dim.a16.ll
…
llvm.amdgcn.image.atomic.dim.ll
…
llvm.amdgcn.image.atomic.dim.mir
[AMDGPU][MC] Fix disassembler problem for image_atomic with TFE (#112622)
2024-10-24 16:19:18 -07:00
llvm.amdgcn.image.gather4.a16.dim.ll
…
llvm.amdgcn.image.gather4.dim.ll
…
llvm.amdgcn.image.gather4.o.dim.ll
…
llvm.amdgcn.image.getresinfo.a16.ll
…
llvm.amdgcn.image.getresinfo.ll
…
llvm.amdgcn.image.load.1d.d16.ll
…
llvm.amdgcn.image.load.1d.ll
…
llvm.amdgcn.image.load.2d.ll
…
llvm.amdgcn.image.load.2darraymsaa.a16.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.2darraymsaa.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.load.3d.a16.ll
…
llvm.amdgcn.image.load.3d.ll
[AMDGPU] CodeGen for GFX12 S_WAIT_* instructions (#77438)
2024-01-18 10:47:45 +00:00
llvm.amdgcn.image.sample.cd.g16.ll
…
llvm.amdgcn.image.sample.g16.ll
…
llvm.amdgcn.image.store.2d.d16.ll
…
llvm.amdgcn.image.store.2d.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.implicit.ptr.buffer.ll
[AMDGPU] Add buffer intrinsics that take resources as pointers
2023-06-05 16:59:07 +00:00
llvm.amdgcn.interp.inreg.ll
[AMDGPU] Expose RTZ version of f16 interpolation for gfx11+ (#86614)
2024-04-01 09:48:37 +08:00
llvm.amdgcn.interp.p1.f16.ll
…
llvm.amdgcn.intersect_ray.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
llvm.amdgcn.kernarg.segment.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.make.buffer.rsrc.ll
…
llvm.amdgcn.mfma.gfx90a.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
llvm.amdgcn.mov.dpp.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.queue.ptr.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.raw.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.atomic.cmpswap.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
llvm.amdgcn.raw.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.raw.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.format.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.buffer.load.tfe.ll
[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)
2024-05-27 14:09:17 +02:00
llvm.amdgcn.raw.buffer.store.format.f16.ll
…
llvm.amdgcn.raw.buffer.store.format.f32.ll
…
llvm.amdgcn.raw.buffer.store.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.atomic.cmpswap.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.raw.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.format.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.load.ll
[AMDGPU] Allow buffer intrinsics to be marked volatile at the IR level (#77847)
2024-01-12 11:20:01 -06:00
llvm.amdgcn.raw.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.buffer.store.ll
[AMDGPU] Allow buffer intrinsics to be marked volatile at the IR level (#77847)
2024-01-12 11:20:01 -06:00
llvm.amdgcn.raw.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.raw.ptr.tbuffer.store.f16.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.i8.ll
…
llvm.amdgcn.raw.ptr.tbuffer.store.ll
…
llvm.amdgcn.raw.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.raw.tbuffer.store.f16.ll
…
llvm.amdgcn.raw.tbuffer.store.i8.ll
…
llvm.amdgcn.raw.tbuffer.store.ll
…
llvm.amdgcn.rsq.clamp.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
llvm.amdgcn.s.buffer.load.ll
[AMDGPU][GISel] Use datalayout alignment for buffer-load legalization (#95578)
2024-06-15 18:19:52 +05:30
llvm.amdgcn.s.setreg.ll
…
llvm.amdgcn.s.sleep.ll
…
llvm.amdgcn.sbfe.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.sdot2.ll
…
llvm.amdgcn.sdot4.ll
…
llvm.amdgcn.sdot8.ll
…
llvm.amdgcn.set.inactive.ll
[AMDGPU] Simplify and improve codegen for llvm.amdgcn.set.inactive (#107889)
2024-09-11 17:16:06 +01:00
llvm.amdgcn.softwqm.ll
…
llvm.amdgcn.struct.buffer.atomic.add.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.atomic.cmpswap.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
llvm.amdgcn.struct.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.struct.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.buffer.load.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.buffer.load.ll
[AMDGPU] Fix broken sign-extended subword buffer load combine (#77470)
2024-01-10 10:50:13 +00:00
llvm.amdgcn.struct.buffer.load.tfe.ll
[AMDGPU] Legalize and select raw/struct_buffer_load with tfe (#93310)
2024-05-27 14:09:17 +02:00
llvm.amdgcn.struct.buffer.store.format.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.format.f32.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.buffer.store.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.ptr.buffer.atomic.add.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.atomic.cmpswap.ll
[AMDGPU] CodeGen for 64-bit buffer atomic cmpswap intrinsics (#70475)
2023-10-30 16:44:22 +00:00
llvm.amdgcn.struct.ptr.buffer.atomic.fadd-with-ret.ll
…
llvm.amdgcn.struct.ptr.buffer.atomic.fadd.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.load.format.ll
[AMDGPU] Extend zero initialization of return values for TFE (#85759)
2024-03-25 09:01:46 +00:00
llvm.amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.format.f32.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.f16.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.ptr.tbuffer.load.ll
[GlobalISel] Add dead flags to implicit defs in ISel
2023-08-09 14:20:51 +02:00
llvm.amdgcn.struct.tbuffer.load.f16.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.struct.tbuffer.load.ll
[AMDGPU] CodeGen for GFX12 VBUFFER instructions (#75492)
2023-12-15 13:45:03 +01:00
llvm.amdgcn.sudot4.ll
…
llvm.amdgcn.sudot8.ll
…
llvm.amdgcn.trig.preop.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.ubfe.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.udot2.ll
…
llvm.amdgcn.udot4.ll
…
llvm.amdgcn.udot8.ll
…
llvm.amdgcn.update.dpp.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wmma_32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.wmma_64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
llvm.amdgcn.workgroup.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.workitem.id.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
llvm.amdgcn.wqm.demote.ll
[AMDGPU] Remove -wavefrontsizeX from GlobalISel tests (NFC) (#100812)
2024-07-28 11:26:29 +04:00
llvm.amdgcn.wqm.ll
…
llvm.amdgcn.writelane.ll
…
llvm.amdgcn.wwm.ll
…
llvm.memcpy.inline.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
llvm.memcpy.ll
[AMDGPU] Use wider loop lowering type for LowerMemIntrinsics (#112332)
2024-10-28 09:04:19 +01:00
llvm.memmove.ll
[LowerMemIntrinsics] Lower llvm.memmove to wide memory accesses (#100122)
2024-07-26 08:43:30 +02:00
llvm.memset.ll
AMDGPU/GlobalISel: Partially move constant selection to patterns (#100786)
2024-07-30 18:18:16 +04:00
llvm.powi.ll
[AMDGPU][True16][CodeGen] fp conversion in true/fake16 format (#101678)
2024-10-16 12:26:01 -04:00
load-constant32bit.ll
AMDGPU: Bulk update all GlobalISel tests to use opaque pointers
2022-11-28 11:51:36 -05:00
load-constant.96.ll
…
load-legalize-range-metadata.ll
GlobalISel: Drop vector range metadata on bitcast lowering (#97279)
2024-07-01 15:26:09 +02:00
load-local.96.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-local.128.ll
AMDGPU/GlobalISel: Insert m0 initialization before sextload/zextload (#111720)
2024-10-10 14:01:49 +04:00
load-unaligned.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
localizer-wrong-insert-point.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
localizer.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
lshr.ll
[GlobalIsel] Push cast through select. (#100539)
2024-07-25 19:21:28 +02:00
madmix-constant-bus-violation.ll
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
madmix-constant-bus-violation.mir
[AMDGPU][GlobalISel] Align selectVOP3PMadMixModsImpl with the SelectionDAG counterpart (#110168)
2024-10-08 09:41:24 -04:00
memory-legalizer-atomic-fence.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
merge-buffer-stores.ll
[SeperateConstOffsetFromGEP] Handle or disjoint flags (#76997)
2024-01-26 09:56:06 -06:00
minmaxabs.ll
[IR] Add min/max/abs intrinsics
2020-07-23 20:56:19 +02:00
mmra.ll
[IR] Memory Model Relaxation Annotations (#78569)
2024-04-24 08:52:25 +02:00
mubuf-global.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
mul-known-bits.i64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
mul-known-bits.i64.mir
…
mul.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
mul.v2i16.ll
…
no-cse-nonlocal-convergent-instrs.mir
[CodeGen][NewPM] Port MachineCSE pass to new pass manager. (#106605)
2024-09-04 18:54:07 +05:30
no-legalize-atomic.mir
…
non-entry-alloca.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
orn2.ll
[GISel][AArch64] Combine G_BUILD_VECTOR(G_UNMERGE) with undef elements
2023-08-22 14:25:31 +01:00
postlegalizer-combiner-buildvector-identities.mir
…
postlegalizer-combiner-divrem.mir
…
postlegalizer-combiner-fcanonicalize.mir
…
postlegalizer-combiner-freeze.mir
…
postlegalizer-combiner-reassoc.mir
…
postlegalizer-combiner-sextload-from-sextinreg.mir
…
postlegalizer-combiner-trunc-bitcast-buildvector.mir
…
postlegalizer-combiner-unmerge-undef.mir
…
postlegalizer-combiner-zextload-from-and.mir
…
postlegalizercombiner-and.mir
[AMDGPU][GlobalISel] Disable fixed-point iteration in all Combiners (#105517)
2024-08-22 17:14:53 +01:00
postlegalizercombiner-ashr.mir
…
postlegalizercombiner-load-and-mask.mir
…
postlegalizercombiner-lshr.mir
…
postlegalizercombiner-mul.mir
…
postlegalizercombiner-sbfx.mir
…
postlegalizercombiner-select.mir
…
postlegalizercombiner-shl.mir
…
postlegalizercombiner-ubfx.mir
…
prelegalizer-combiner-divrem.mir
…
prelegalizer-combiner-fptrunc_fpext.mir
…
prelegalizer-combiner-redundant-bitcast.mir
…
prelegalizer-combiner-sext_inreg-to-and.mir
…
regbankcombiner-clamp-fmed3-const.mir
…
regbankcombiner-clamp-minmax-const.mir
…
regbankcombiner-fmed3-minmax-const.mir
…
regbankcombiner-redundant-and.mir
AMDGPU/GlobalISel: Run redundant_and combine in RegBankCombiner (#112353)
2024-10-16 09:43:16 +02:00
regbankcombiner-smed3.mir
…
regbankcombiner-umed3.mir
…
regbankselect-abs.mir
…
regbankselect-add.s16.mir
…
regbankselect-add.s32.mir
…
regbankselect-add.v2s16.mir
…
regbankselect-amdgcn-exp-compr.mir
…
regbankselect-amdgcn-exp.mir
…
regbankselect-amdgcn-s-buffer-load.mir
…
regbankselect-amdgcn.ballot.i64.mir
…
regbankselect-amdgcn.class.mir
…
regbankselect-amdgcn.cvt.pkrtz.mir
…
regbankselect-amdgcn.div.fmas.mir
…
regbankselect-amdgcn.div.scale.mir
…
regbankselect-amdgcn.ds.append.mir
…
regbankselect-amdgcn.ds.bpermute.mir
…
regbankselect-amdgcn.ds.consume.mir
…
regbankselect-amdgcn.ds.gws.init.mir
…
regbankselect-amdgcn.ds.gws.sema.v.mir
…
regbankselect-amdgcn.ds.ordered.add.mir
…
regbankselect-amdgcn.ds.ordered.swap.mir
…
regbankselect-amdgcn.ds.permute.mir
…
regbankselect-amdgcn.ds.swizzle.mir
…
regbankselect-amdgcn.else.32.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
regbankselect-amdgcn.else.64.mir
[AMDGPU] don't mark control-flow intrinsics as convergent (#90026)
2024-05-06 14:07:11 +05:30
regbankselect-amdgcn.fcmp.mir
…
regbankselect-amdgcn.fmul.legacy.mir
…
regbankselect-amdgcn.groupstaticsize.mir
…
regbankselect-amdgcn.icmp.mir
…
regbankselect-amdgcn.image.load.1d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regbankselect-amdgcn.image.sample.1d.ll
AMDGPU: Regenerate baseline mir tests
2024-02-27 10:44:53 +05:30
regbankselect-amdgcn.interp.mov.mir
…
regbankselect-amdgcn.interp.p1.f16.mir
…
regbankselect-amdgcn.interp.p1.mir
…
regbankselect-amdgcn.interp.p2.f16.mir
…
regbankselect-amdgcn.interp.p2.mir
…
regbankselect-amdgcn.kernarg.segment.ptr.mir
…
regbankselect-amdgcn.kill.mir
…
regbankselect-amdgcn.lds.direct.load.mir
…
regbankselect-amdgcn.lds.param.load.mir
…
regbankselect-amdgcn.live.mask.mir
…
regbankselect-amdgcn.mfma.gfx90a.mir
…
regbankselect-amdgcn.mfma.gfx940.mir
…
regbankselect-amdgcn.mfma.mir
…
regbankselect-amdgcn.ps.live.mir
…
regbankselect-amdgcn.raw.buffer.load.ll
…
regbankselect-amdgcn.raw.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.readfirstlane.mir
…
regbankselect-amdgcn.readlane.mir
…
regbankselect-amdgcn.s.buffer.load.ll
[AMDGPU][GISel] Use datalayout alignment for buffer-load legalization (#95578)
2024-06-15 18:19:52 +05:30
regbankselect-amdgcn.s.buffer.load.mir
…
regbankselect-amdgcn.s.get.waveid.in.workgroup.mir
…
regbankselect-amdgcn.s.getpc.mir
…
regbankselect-amdgcn.s.getreg.mir
…
regbankselect-amdgcn.s.memrealtime.mir
…
regbankselect-amdgcn.s.memtime.mir
…
regbankselect-amdgcn.s.sendmsg.mir
…
regbankselect-amdgcn.s.sendmsghalt.mir
…
regbankselect-amdgcn.struct.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.buffer.store.ll
…
regbankselect-amdgcn.struct.ptr.buffer.load.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.struct.ptr.buffer.store.ll
[GlobalISel] convergent intrinsics
2023-07-31 12:15:39 +05:30
regbankselect-amdgcn.update.dpp.mir
…
regbankselect-amdgcn.wqm.demote.mir
…
regbankselect-amdgcn.wqm.mir
…
regbankselect-amdgcn.wqm.vote.mir
…
regbankselect-amdgcn.writelane.mir
…
regbankselect-amdgcn.wwm.mir
…
regbankselect-amdgpu-ffbh-u32.mir
…
regbankselect-amdgpu-ffbl-b32.mir
…
regbankselect-amdgpu-wave-address.mir
…
regbankselect-and-s1.mir
…
regbankselect-and.mir
…
regbankselect-anyext.mir
…
regbankselect-ashr.mir
…
regbankselect-assert-align.mir
…
regbankselect-assert-zext.mir
…
regbankselect-atomic-cmpxchg.mir
…
regbankselect-atomicrmw-add.mir
…
regbankselect-atomicrmw-and.mir
…
regbankselect-atomicrmw-fadd.mir
…
regbankselect-atomicrmw-max.mir
…
regbankselect-atomicrmw-min.mir
…
regbankselect-atomicrmw-or.mir
…
regbankselect-atomicrmw-sub.mir
…
regbankselect-atomicrmw-umax.mir
…
regbankselect-atomicrmw-umin.mir
…
regbankselect-atomicrmw-xchg.mir
…
regbankselect-atomicrmw-xor.mir
…
regbankselect-bitcast.mir
…
regbankselect-bitreverse.mir
…
regbankselect-block-addr.mir
…
regbankselect-brcond.mir
…
regbankselect-bswap.mir
…
regbankselect-build-vector.mir
…
regbankselect-concat-vector.mir
…
regbankselect-constant.mir
…
regbankselect-copy.mir
[AMDGPU] Set register bank for i1 register copies (#96155)
2024-08-07 10:34:09 -07:00
regbankselect-ctlz-zero-undef.mir
…
regbankselect-ctpop.mir
…
regbankselect-cttz-zero-undef.mir
…
regbankselect-default.mir
…
regbankselect-dyn-stackalloc.mir
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
regbankselect-extract-vector-elt.mir
…
regbankselect-extract.mir
…
regbankselect-fabs.mir
…
regbankselect-fadd.mir
…
regbankselect-fcanonicalize.mir
…
regbankselect-fceil.mir
…
regbankselect-fcmp.mir
…
regbankselect-fexp2.mir
…
regbankselect-flog2.mir
…
regbankselect-fma.mir
…
regbankselect-fmul.mir
…
regbankselect-fneg.mir
…
regbankselect-fpext.mir
…
regbankselect-fptosi.mir
…
regbankselect-fptoui.mir
…
regbankselect-fptrunc.mir
…
regbankselect-frame-index.mir
AMDGPU/GlobalISel: Permit mapping G_FRAME_INDEX to sgprs (#101325)
2024-08-01 09:42:04 +04:00
regbankselect-freeze.mir
…
regbankselect-fshr.mir
…
regbankselect-fsqrt.mir
…
regbankselect-fsub.mir
…
regbankselect-icmp.mir
…
regbankselect-icmp.s16.mir
…
regbankselect-illegal-copy.mir
…
regbankselect-implicit-def.mir
…
regbankselect-insert-vector-elt.mir
…
regbankselect-insert.mir
…
regbankselect-intrinsic-trunc.mir
…
regbankselect-inttoptr.mir
…
regbankselect-load.mir
…
regbankselect-lshr.mir
…
regbankselect-mad_64_32.mir
…
regbankselect-merge-values.mir
…
regbankselect-mul.mir
…
regbankselect-or.mir
AMDGPU: Preserve flags in regbankselect when splitting or
2024-10-02 12:08:21 +04:00
regbankselect-phi-s1.mir
…
regbankselect-phi.mir
…
regbankselect-pseudo-scalar-transcendental.mir
…
regbankselect-ptr-add.mir
…
regbankselect-ptrmask.mir
…
regbankselect-ptrtoint.mir
…
regbankselect-reg-sequence.mir
…
regbankselect-sadde.mir
…
regbankselect-salu-float.mir
…
regbankselect-sbfx.mir
…
regbankselect-select.mir
AMDGPU/GlobalISel: Preserve flags when splitting select
2024-10-02 12:08:17 +04:00
regbankselect-sext-inreg.mir
…
regbankselect-sext.mir
…
regbankselect-sextload.mir
…
regbankselect-shl.mir
…
regbankselect-sitofp.mir
…
regbankselect-smax.mir
…
regbankselect-smin.mir
…
regbankselect-smulh.mir
…
regbankselect-split-scalar-load-metadata.mir
…
regbankselect-ssube.mir
…
regbankselect-sub.mir
…
regbankselect-trunc.mir
…
regbankselect-uadde.mir
…
regbankselect-uaddo.mir
…
regbankselect-ubfx.mir
…
regbankselect-uitofp.mir
…
regbankselect-umax.mir
…
regbankselect-umin.mir
…
regbankselect-umulh.mir
…
regbankselect-uniform-load-noclobber.mir
…
regbankselect-unmerge-values.mir
…
regbankselect-usube.mir
…
regbankselect-usubo.mir
…
regbankselect-waterfall-agpr.mir
…
regbankselect-widen-scalar-loads.mir
…
regbankselect-xor.mir
…
regbankselect-zext.mir
…
regbankselect-zextload.mir
…
regbankselect.mir
Reland "[AMDGPU][GlobalIsel] Use isRegisterClassType for G_FREEZE and G_IMPLICIT_DEF (#101331)" (#109958)
2024-09-25 13:02:29 +02:00
saddsat.ll
[AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800)
2024-06-14 19:14:19 +02:00
sbfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
sdiv.i32.ll
[GlobalISel] Handle div-by-pow2 (#83155)
2024-03-29 12:41:47 -04:00
sdiv.i64.ll
[GlobalISel] Support vector G_UNMERGE_VALUES in computeKnownBits. (#112172)
2024-10-15 08:23:05 +01:00
sdivrem.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
select-to-fmin-fmax.ll
…
sext_inreg.ll
…
shader-epilogs.ll
…
shl-ext-reduce.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
shl.ll
[GlobalIsel] Push cast through select. (#100539)
2024-07-25 19:21:28 +02:00
shlN_add.ll
…
smed3.ll
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
smrd.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
srem.i32.ll
…
srem.i64.ll
[GlobalISel] Support vector G_UNMERGE_VALUES in computeKnownBits. (#112172)
2024-10-15 08:23:05 +01:00
ssubsat.ll
[AMDGPU] Adding multiple use analysis to SIPeepholeSDWA (#94800)
2024-06-14 19:14:19 +02:00
store-local.96.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
store-local.128.ll
Reapply "AMDGPU: Move attributor into optimization pipeline (#83131)" and follow up commit "clang/AMDGPU: Defeat attribute optimization in attribute test" (#98851)
2024-07-15 11:51:44 +04:00
strict_fma.f16.ll
…
strict_fma.f32.ll
…
strict_fma.f64.ll
…
sub.v2i16.ll
AMDGPU: Materialize bitwise not of inline immediates (#95960)
2024-06-22 00:40:59 +02:00
subo.ll
[AMDGPU,test] Change llc -march= to -mtriple= (#75982)
2024-01-16 21:54:58 -08:00
trunc.ll
[AMDGPU] Aggressively fold immediates in SIShrinkInstructions
2022-05-18 11:04:33 +01:00
twoaddr-extract-dyn-v7f64.mir
[llc] Provide opt like verifier options (#106665)
2024-09-04 17:37:34 +08:00
uaddsat.ll
[GISel][CombinerHelper] Combine op(trunc(x), trunc(y)) -> trunc(op(x, y)) (#89023)
2024-06-03 10:42:10 +05:30
ubfx.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00
udiv.i32.ll
…
udiv.i64.ll
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
udivrem.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
umed3.ll
[GlobalISel] Handle more commutable instructions in commute_constant_to_rhs
2024-04-16 02:36:12 -04:00
unsupported-load.ll
…
unsupported-ptr-add.ll
…
urem.i32.ll
…
urem.i64.ll
[GlobalIsel] Combine trunc of binop (#107721)
2024-09-11 15:04:55 +02:00
usubsat.ll
[GISel][CombinerHelper] Combine op(trunc(x), trunc(y)) -> trunc(op(x, y)) (#89023)
2024-06-03 10:42:10 +05:30
v_bfe_i32.ll
…
vni8-across-blocks.ll
[AMDGPU][MC] Disallow null as saddr in flat instructions (#101730)
2024-09-24 11:08:41 +04:00
widen-i8-i16-scalar-loads.ll
[AMDGPU] Codegen support for constrained multi-dword sloads (#96163)
2024-07-23 13:59:15 +05:30
wmma-gfx12-w32-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w32.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-f16-f32-matrix-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-imm.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-iu-modifiers.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64-swmmac-index_key.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
wmma-gfx12-w64.ll
[AMDGPU] Skip VGPR deallocation for waveslot limited kernels (#112765)
2024-10-21 09:39:52 -07:00
xnor.ll
[GISel][CombinerHelper] Combine op(trunc(x), trunc(y)) -> trunc(op(x, y)) (#89023)
2024-06-03 10:42:10 +05:30
zextload.ll
[AMDGPU] Do not wait for vscnt on function entry and return
2023-07-04 12:22:38 +01:00