229e118559
For targets that support xnack replay feature (gfx8+), the multi-dword scalar loads shouldn't clobber any register that holds the src address. The constrained version of the scalar loads have the early clobber flag attached to the dst operand to restrict RA from re-allocating any of the src regs for its dst operand.
118 lines
4.8 KiB
LLVM
118 lines
4.8 KiB
LLVM
; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=SI,GCN %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=bonaire -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=CI,GCN,SICIVI %s
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; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga -show-mc-encoding -verify-machineinstrs -global-isel | FileCheck --check-prefixes=VI,GCN,SICIVI %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx900 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s
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; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 -show-mc-encoding -verify-machineinstrs -global-isel < %s | FileCheck --check-prefixes=GFX9_10,GCN,VIGFX9_10,SIVIGFX9_10 %s
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; SMRD load with an immediate offset.
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; GCN-LABEL: {{^}}smrd0:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x1 ; encoding: [0x01
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; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x4
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define amdgpu_kernel void @smrd0(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 1
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; SMRD load with the largest possible immediate offset.
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; GCN-LABEL: {{^}}smrd1:
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; SICI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xff ; encoding: [0xff,0x{{[0-9]+[137]}}
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; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3fc
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define amdgpu_kernel void @smrd1(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 255
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate.
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; GCN-LABEL: {{^}}smrd2:
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; SI: s_movk_i32 s[[OFFSET:[0-9]]], 0x400
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], s[[OFFSET]] ; encoding: [0x0[[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x100
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; VIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x400
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd2(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 256
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; SMRD load with a 64-bit offset
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; GCN-LABEL: {{^}}smrd3:
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; FIXME: There are too many copies here because we don't fold immediates
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; through REG_SEQUENCE
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; XSI: s_load_dwordx2 s[{{[0-9]:[0-9]}}], s[{{[0-9]:[0-9]}}], 0xb ; encoding: [0x0b
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; TODO: Add VI checks
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; XGCN: s_endpgm
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define amdgpu_kernel void @smrd3(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 4294967296 ; 2 ^ 32
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; SMRD load with the largest possible immediate offset on VI
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; GCN-LABEL: {{^}}smrd4:
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; SI: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; SI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x3ffff
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; VI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0xffffc
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; GFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0xffffc
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; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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define amdgpu_kernel void @smrd4(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 262143
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; SMRD load with an offset greater than the largest possible immediate on VI
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; GCN-LABEL: {{^}}smrd5:
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; SIVIGFX9_10: s_mov_b32 [[OFFSET:s[0-9]+]], 0x100000
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; SIVIGFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], [[OFFSET]]
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; CI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x40000
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; GCN: s_endpgm
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define amdgpu_kernel void @smrd5(ptr addrspace(4) %ptr) {
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entry:
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%0 = getelementptr i32, ptr addrspace(4) %ptr, i64 262144
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%1 = load i32, ptr addrspace(4) %0
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store i32 %1, ptr addrspace(1) undef
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ret void
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}
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; GFX9+ can use a signed immediate byte offset but not without sgpr[offset]
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; GCN-LABEL: {{^}}smrd6:
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; SICIVI: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, -4
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; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
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; GFX9_10: s_add_u32 s0, s6, -4
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; GFX9_10: s_addc_u32 s1, s7, -1
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; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
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define amdgpu_kernel void @smrd6(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {
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entry:
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%tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -1
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%tmp1 = load i32, ptr addrspace(4) %tmp
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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; Don't use a negative SGPR offset
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; GCN-LABEL: {{^}}smrd7:
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; GCN: s_add_u32 s{{[0-9]}}, s{{[0-9]}}, 0xffe00000
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; SICIVI: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
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; GFX9_10: s_load_dword s{{[0-9]}}, s[{{[0-9]:[0-9]}}], 0x0
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define amdgpu_kernel void @smrd7(ptr addrspace(1) %out, ptr addrspace(4) %ptr) #0 {
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entry:
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%tmp = getelementptr i32, ptr addrspace(4) %ptr, i64 -524288
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%tmp1 = load i32, ptr addrspace(4) %tmp
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store i32 %tmp1, ptr addrspace(1) %out
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ret void
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}
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