594579b7af
I realized after spending way too much time looking at this, that we can avoid objdump entirely here by having the assembly simply not print the aliases. Once we do that, we can simply autogen this test, and updates become trivial and understandable.
687 lines
21 KiB
LLVM
687 lines
21 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 5
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=+c,+f,+d \
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; RUN: -riscv-no-aliases < %s \
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; RUN: | FileCheck -check-prefix=RV32IFDC %s
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; RUN: llc -mtriple=riscv32 -target-abi ilp32d -mattr=-c,+f,+d \
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; RUN: -riscv-no-aliases < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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; constant is small and fit in 6 bit (compress imm)
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define i32 @ne_small_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_small_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a2, 20
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB0_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB0_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_small_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 20
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB0_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB0_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 20
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is small and fit in 6 bit (compress imm)
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define i32 @ne_small_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_small_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a2, -20
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB1_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB1_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_small_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -20
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB1_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB1_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -20
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is small and fit in 6 bit (compress imm)
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define i32 @ne_small_edge_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_small_edge_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a2, 31
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB2_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB2_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_small_edge_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 31
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB2_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB2_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 31
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is small and fit in 6 bit (compress imm)
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define i32 @ne_small_edge_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_small_edge_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a2, -32
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB3_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB3_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_small_edge_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -32
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB3_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB3_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -32
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm)
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define i32 @ne_medium_ledge_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_ledge_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, -33
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB4_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB4_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_ledge_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 33
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB4_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB4_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 33
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm)
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define i32 @ne_medium_ledge_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_ledge_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, 33
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB5_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB5_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_ledge_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -33
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB5_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB5_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -33
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm)
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define i32 @ne_medium_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, -63
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB6_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB6_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 63
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB6_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB6_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 63
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm)
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define i32 @ne_medium_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, 63
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB7_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB7_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -63
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB7_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB7_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -63
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm)
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define i32 @ne_medium_bedge_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_bedge_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, -2047
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB8_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB8_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_bedge_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 2047
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB8_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB8_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 2047
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is medium and not fit in 6 bit (compress imm),
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; but fit in 12 bit (imm), negative value fit in 12 bit too.
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define i32 @ne_medium_bedge_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_medium_bedge_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: addi a1, a0, 2047
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: c.bnez a1, .LBB9_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB9_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_medium_bedge_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -2047
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB9_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB9_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -2047
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is big and do not fit in 12 bit (imm), fit in i32
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define i32 @ne_big_ledge_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_big_ledge_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a0, 1
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; RV32IFDC-NEXT: slli a2, a0, 11
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB10_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB10_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_big_ledge_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a0, zero, 1
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; RV32IFD-NEXT: slli a2, a0, 11
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB10_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB10_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, 2048
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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; constant is big and do not fit in 12 bit (imm), fit in i32
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define i32 @ne_big_ledge_neg(i32 %in0) minsize {
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; RV32IFDC-LABEL: ne_big_ledge_neg:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: addi a2, zero, -2048
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: bne a1, a2, .LBB11_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB11_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: ne_big_ledge_neg:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, -2048
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: bne a1, a2, .LBB11_2
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; RV32IFD-NEXT: # %bb.1:
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; RV32IFD-NEXT: addi a0, zero, 42
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; RV32IFD-NEXT: .LBB11_2:
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; RV32IFD-NEXT: jalr zero, 0(ra)
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%cmp = icmp ne i32 %in0, -2048
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%toRet = select i1 %cmp, i32 -99, i32 42
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ret i32 %toRet
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}
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;; Same as above, but for eq
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; constant is small and fit in 6 bit (compress imm)
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define i32 @eq_small_pos(i32 %in0) minsize {
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; RV32IFDC-LABEL: eq_small_pos:
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; RV32IFDC: # %bb.0:
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; RV32IFDC-NEXT: c.mv a1, a0
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; RV32IFDC-NEXT: c.li a2, 20
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; RV32IFDC-NEXT: addi a0, zero, -99
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; RV32IFDC-NEXT: beq a1, a2, .LBB12_2
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; RV32IFDC-NEXT: # %bb.1:
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; RV32IFDC-NEXT: addi a0, zero, 42
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; RV32IFDC-NEXT: .LBB12_2:
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; RV32IFDC-NEXT: c.jr ra
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;
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; RV32IFD-LABEL: eq_small_pos:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: addi a1, a0, 0
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; RV32IFD-NEXT: addi a2, zero, 20
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; RV32IFD-NEXT: addi a0, zero, -99
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; RV32IFD-NEXT: beq a1, a2, .LBB12_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB12_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 20
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is small and fit in 6 bit (compress imm)
|
|
define i32 @eq_small_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_small_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: c.mv a1, a0
|
|
; RV32IFDC-NEXT: c.li a2, -20
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: beq a1, a2, .LBB13_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB13_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_small_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -20
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB13_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB13_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -20
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is small and fit in 6 bit (compress imm)
|
|
define i32 @eq_small_edge_pos(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_small_edge_pos:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: c.mv a1, a0
|
|
; RV32IFDC-NEXT: c.li a2, 31
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: beq a1, a2, .LBB14_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB14_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_small_edge_pos:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, 31
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB14_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB14_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 31
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is small and fit in 6 bit (compress imm)
|
|
define i32 @eq_small_edge_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_small_edge_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: c.mv a1, a0
|
|
; RV32IFDC-NEXT: c.li a2, -32
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: beq a1, a2, .LBB15_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB15_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_small_edge_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -32
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB15_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB15_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -32
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm)
|
|
define i32 @eq_medium_ledge_pos(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_ledge_pos:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, -33
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB16_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB16_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_ledge_pos:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, 33
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB16_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB16_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 33
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm)
|
|
define i32 @eq_medium_ledge_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_ledge_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, 33
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB17_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB17_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_ledge_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -33
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB17_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB17_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -33
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm)
|
|
define i32 @eq_medium_pos(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_pos:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, -63
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB18_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB18_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_pos:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, 63
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB18_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB18_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 63
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm)
|
|
define i32 @eq_medium_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, 63
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB19_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB19_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -63
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB19_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB19_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -63
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm)
|
|
define i32 @eq_medium_bedge_pos(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_bedge_pos:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, -2047
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB20_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB20_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_bedge_pos:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, 2047
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB20_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB20_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 2047
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is medium and not fit in 6 bit (compress imm),
|
|
; but fit in 12 bit (imm), negative value fit in 12 bit too.
|
|
define i32 @eq_medium_bedge_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_medium_bedge_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: addi a1, a0, 2047
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: c.beqz a1, .LBB21_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB21_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_medium_bedge_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -2047
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB21_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB21_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -2047
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is big and do not fit in 12 bit (imm), fit in i32
|
|
define i32 @eq_big_ledge_pos(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_big_ledge_pos:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: c.mv a1, a0
|
|
; RV32IFDC-NEXT: c.li a0, 1
|
|
; RV32IFDC-NEXT: slli a2, a0, 11
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: beq a1, a2, .LBB22_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB22_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_big_ledge_pos:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a0, zero, 1
|
|
; RV32IFD-NEXT: slli a2, a0, 11
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB22_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB22_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, 2048
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|
|
|
|
; constant is big and do not fit in 12 bit (imm), fit in i32
|
|
define i32 @eq_big_ledge_neg(i32 %in0) minsize {
|
|
; RV32IFDC-LABEL: eq_big_ledge_neg:
|
|
; RV32IFDC: # %bb.0:
|
|
; RV32IFDC-NEXT: c.mv a1, a0
|
|
; RV32IFDC-NEXT: addi a2, zero, -2048
|
|
; RV32IFDC-NEXT: addi a0, zero, -99
|
|
; RV32IFDC-NEXT: beq a1, a2, .LBB23_2
|
|
; RV32IFDC-NEXT: # %bb.1:
|
|
; RV32IFDC-NEXT: addi a0, zero, 42
|
|
; RV32IFDC-NEXT: .LBB23_2:
|
|
; RV32IFDC-NEXT: c.jr ra
|
|
;
|
|
; RV32IFD-LABEL: eq_big_ledge_neg:
|
|
; RV32IFD: # %bb.0:
|
|
; RV32IFD-NEXT: addi a1, a0, 0
|
|
; RV32IFD-NEXT: addi a2, zero, -2048
|
|
; RV32IFD-NEXT: addi a0, zero, -99
|
|
; RV32IFD-NEXT: beq a1, a2, .LBB23_2
|
|
; RV32IFD-NEXT: # %bb.1:
|
|
; RV32IFD-NEXT: addi a0, zero, 42
|
|
; RV32IFD-NEXT: .LBB23_2:
|
|
; RV32IFD-NEXT: jalr zero, 0(ra)
|
|
%cmp = icmp eq i32 %in0, -2048
|
|
%toRet = select i1 %cmp, i32 -99, i32 42
|
|
ret i32 %toRet
|
|
}
|