Harald van Dijk 950ee75909 [RISC-V] Fix check of minimum vlen. (#114055) ...

If we have a minimum vlen, we were adjusting StackSize to change the
unit from vscale to bytes, and then calculating the required padding
size for alignment in bytes. However, we then used that padding size as
an offset in vscale units, resulting in misplaced stack objects.

While it would be possible to adjust the object offsets by dividing
AlignmentPadding by ST.getRealMinVLen() / RISCV::RVVBitsPerBlock, we can
simplify the calculation a bit if instead we adjust the alignment to be
in vscale units.

@topperc This fixes a bug I am seeing after #110312, but I am not 100%
certain I am understanding the code correctly, could you please see if
this makes sense to you?

2024-10-29 17:30:30 +00:00

..

GlobalISel

[RISCV][GISEL] Fix operand on RISCV::G_VMV_V_V_VL

2024-10-21 06:58:12 -07:00

intrinsics

…

rvv

[RISC-V] Fix check of minimum vlen. (#114055)

2024-10-29 17:30:30 +00:00

abds-neg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

abds.ll

Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)

2024-10-15 21:07:06 +08:00

abdu-neg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

abdu.ll

Reapply "[DAG] Enhance SDPatternMatch to match integer minimum and maximum patterns in addition to the existing ISD nodes." (#112203)

2024-10-15 21:07:06 +08:00

add-before-shl.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

add-imm.ll

…

addc-adde-sube-subc.ll

…

addcarry.ll

…

addimm-mulimm.ll

…

addrspacecast.ll

…

aext-to-sext.ll

…

aext.ll

…

align-loops.ll

…

align.ll

…

alloca.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

allow-check.ll

…

alu8.ll

…

alu16.ll

…

alu32.ll

…

alu64.ll

…

analyze-branch.ll

…

and-add-lsr.ll

…

and.ll

…

arith-with-overflow.ll

…

atomic-cmpxchg-branch-on-result.ll

[RISCV] Mark Zacas as non-experimental (#109651)

2024-09-25 06:14:43 +01:00

atomic-cmpxchg-flag.ll

…

atomic-cmpxchg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

atomic-fence.ll

Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

2024-07-09 10:45:56 -07:00

atomic-load-store.ll

Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

2024-07-09 10:45:56 -07:00

atomic-rmw-discard.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

atomic-rmw-sub.ll

…

atomic-rmw.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

atomic-signext.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

atomicrmw-cond-sub-clamp.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

atomicrmw-uinc-udec-wrap.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

attributes-module-flag.ll

[RISCV] Make M imply Zmmul (#95070)

2024-06-21 11:11:10 +08:00

attributes.ll

[RISCV] Mark RVB23U64 and RVB23S64 as non-experimental (#113918)

2024-10-29 07:57:34 +00:00

avgceils.ll

[RISCV] Add scalar type test coverage for ISD::AVG nodes

2024-06-15 16:15:50 +01:00

avgceilu.ll

[RISCV] Add scalar type test coverage for ISD::AVG nodes

2024-06-15 16:15:50 +01:00

avgfloors.ll

[RISCV] Add scalar type test coverage for ISD::AVG nodes

2024-06-15 16:15:50 +01:00

avgflooru.ll

Recommit "[DAG] Reducing instructions by better legalization handling of AVGFLOORU for illegal data types" (#101223)

2024-07-30 19:00:46 -07:00

bf16-promote.ll

…

bfloat-arith.ll

[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)

2024-09-02 22:04:09 -07:00

bfloat-br-fcmp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-convert.ll

[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)

2024-09-03 15:34:25 -07:00

bfloat-fcmp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-frem.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-imm.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-isnan.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-mem.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

bfloat-select-fcmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

bfloat-select-icmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

bfloat.ll

…

bitextract-mac.ll

…

bitreverse-shift.ll

…

bittest.ll

…

blockaddress.ll

…

branch_zero.ll

…

branch-on-zero.ll

…

branch-opt.ll

…

branch-opt.mir

…

branch-relaxation.ll

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

branch.ll

…

bswap-bitreverse.ll

…

bswap-shift.ll

…

byval.ll

…

callee-saved-fpr32s.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

callee-saved-fpr64s.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

callee-saved-gprs.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-half.ll

[RISCV] Add constant folding combine for FMV_X_ANYEXTW/H. (#106653)

2024-08-30 09:43:42 -07:00

calling-conv-ilp32-ilp32f-common.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-ilp32-ilp32f-ilp32d-common.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-ilp32.ll

…

calling-conv-ilp32d.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-ilp32e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-ilp32f-ilp32d-common.ll

…

calling-conv-lp64-lp64f-common.ll

…

calling-conv-lp64-lp64f-lp64d-common.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-lp64.ll

…

calling-conv-lp64e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-rv32f-ilp32.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-rv32f-ilp32e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-sext-zext.ll

…

calling-conv-vector-float.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

calling-conv-vector-on-stack.ll

…

calls.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

clear-cache.ll

[RISCV] Lower llvm.clear_cache to __riscv_flush_icache for glibc targets (#93481)

2024-06-20 07:27:07 +02:00

cm_mvas_mvsa.ll

…

cm_mvas_mvsa.mir

…

cmov-branch-opt.ll

…

cmp-bool.ll

…

codemodel-lowering.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

compress-double.ll

…

compress-float.ll

…

compress-inline-asm.ll

…

compress-opt-branch.ll

…

compress-opt-select.ll

[RISCV] Autogenerate compress-opt-select.ll

2024-09-17 08:47:20 -07:00

compress.ll

…

condbinops.ll

…

condops.ll

[RISCV] Remove IsRV64 from XVentanaCondOps patterns. (#100891)

2024-07-27 17:26:32 -07:00

convert-highly-predictable-select-to-branch.ll

[RISCV] Add FeaturePredictableSelectIsExpensive

2024-07-05 11:29:42 +08:00

copy-frameindex.mir

…

copyprop.ll

…

copysign-casts.ll

[RISCV] Custom legalize f16/bf16 FCOPYSIGN with Zfhmin/Zbfmin. (#107039)

2024-09-02 22:04:09 -07:00

ctlz-cttz-ctpop.ll

[RISCV] Simplify (srl (and X, Mask), Const) to TH_EXTU (#102802)

2024-08-16 14:23:00 +08:00

ctz_zero_return_test.ll

Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)

2024-08-03 01:51:26 +03:00

disable-tail-calls.ll

…

disjoint.ll

…

div_minsize.ll

…

div-by-constant.ll

…

div-pow2.ll

…

div.ll

[TargetLowering][AMDGPU][ARM][RISCV][X86] Teach SimplifyDemandedBits to combine (srl (sra X, C1), ShAmt) -> sra(X, C1+ShAmt) (#101751)

2024-08-14 08:44:57 -07:00

double_reduct.ll

…

double-arith-strict.ll

…

double-arith.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

double-bitmanip-dagcombines.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

double-br-fcmp.ll

…

double-calling-conv.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

double-convert-strict.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

double-convert.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

double-fcmp-strict.ll

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)

2024-09-12 18:40:52 -07:00

double-fcmp.ll

…

double-frem.ll

…

double-imm.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

double-intrinsics-strict.ll

[Test] Fix usage of constrained intrinsics (#113523)

2024-10-28 14:07:32 +07:00

double-intrinsics.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

double-isnan.ll

…

double-maximum-minimum.ll

…

double-mem.ll

…

double-previous-failure.ll

…

double-round-conv-sat.ll

[DAGCombiner] Push freeze through SETCC and SELECT_CC (#64718)

2024-07-22 16:01:59 +02:00

double-round-conv.ll

[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)

2024-09-05 08:42:13 -07:00

double-select-fcmp.ll

…

double-select-icmp.ll

…

double-stack-spill-restore.ll

…

double-zfa.ll

[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)

2024-09-19 15:16:10 -07:00

dso_local_equivalent.ll

…

dwarf-eh.ll

…

early-clobber-tied-def-subreg-liveness.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

eh-dwarf-cfa.ll

…

elf-preemption.ll

…

emutls.ll

…

exception-pointer-register.ll

…

fastcc-bf16.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-float.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-half.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-int.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fastcc-without-f-reg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixups-diff.ll

…

fli-licm.ll

…

float-arith-strict.ll

…

float-arith.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-bit-preserving-dagcombines.ll

…

float-bitmanip-dagcombines.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-br-fcmp.ll

…

float-convert-strict.ll

[RISCV] Add some Zfinx instructions to hasAllNBitUsers.

2024-08-08 17:33:54 -07:00

float-convert.ll

[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)

2024-09-05 08:42:13 -07:00

float-fcmp-strict.ll

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)

2024-09-12 18:40:52 -07:00

float-fcmp.ll

…

float-frem.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-imm.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-intrinsics-strict.ll

[Test] Fix usage of constrained intrinsics (#113523)

2024-10-28 14:07:32 +07:00

float-intrinsics.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

float-isnan.ll

…

float-maximum-minimum.ll

…

float-mem.ll

…

float-round-conv-sat.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

float-round-conv.ll

…

float-select-fcmp.ll

…

float-select-icmp.ll

…

float-select-verify.ll

…

float-zfa.ll

[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)

2024-09-19 15:16:10 -07:00

flt-rounds.ll

…

fmax-fmin.ll

…

fold-addi-loadstore.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fold-binop-into-select-return-constant.ll

[RISCV] Add a check in lowerSELECT after foldBinOpIntoSelectIfProfitable (#97391)

2024-07-05 10:55:36 +08:00

fold-binop-into-select.ll

…

forced-atomics.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fp16-promote.ll

…

fp128.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fp-fcanonicalize.ll

RISC-V: Select FCANONICALIZE (#112083)

2024-10-14 14:12:36 +08:00

fpclamptosat.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

fpenv.ll

…

frame-info.ll

…

frame.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

frameaddr-returnaddr.ll

…

frm-dependency.ll

…

get-register-invalid.ll

…

get-register-noreserve.ll

…

get-register-reserve.ll

…

get-setcc-result-type.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

ghccc-nest.ll

…

ghccc-rv32.ll

…

ghccc-rv64.ll

…

ghccc-without-f-reg.ll

…

global-merge-minsize-smalldata-nonzero.ll

…

global-merge-minsize-smalldata-zero.ll

…

global-merge-minsize.ll

…

global-merge-offset.ll

…

global-merge.ll

…

graalcc.ll

…

half-arith-strict.ll

[RISCV] Custom legalize f16/bf16 FNEG/FABS with Zfhmin/Zbfmin. (#106886)

2024-08-31 23:57:40 -07:00

half-arith.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

half-bitmanip-dagcombines.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

half-br-fcmp.ll

…

half-convert-strict.ll

[RISCV] Support STRICT_UINT_TO_FP and STRICT_SINT_TO_FP (#102503)

2024-09-17 11:21:52 -03:00

half-convert.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

half-fcmp-strict.ll

[RISCV] Enable floating point CSR alias mnemonics for Zfinx. (#108464)

2024-09-12 18:40:52 -07:00

half-fcmp.ll

…

half-frem.ll

…

half-imm.ll

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

half-intrinsics.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

half-isnan.ll

…

half-maximum-minimum.ll

…

half-mem.ll

…

half-round-conv-sat.ll

[RISCV] Pass f32/f64 directly without a bitcast for Zfinx/Zdinx. (#107464)

2024-09-06 15:50:29 -07:00

half-round-conv.ll

[RISCV] Don't cost Fmv for Zfinx in isFPImmLegal. (#107361)

2024-09-05 08:42:13 -07:00

half-select-fcmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

half-select-icmp.ll

[RISCV] Don't promote f16/bf16 SELECT with Zfhmin/Zfbfmin. (#107138)

2024-09-03 16:04:51 -07:00

half-zfa-fli.ll

…

half-zfa.ll

[RISCV] Move the rest of Zfa FLI instruction handling to lowerConstantFP. (#109217)

2024-09-19 15:16:10 -07:00

hoist-global-addr-base.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

hwasan-check-memaccess.ll

[RISCV] Use RISCVAsmPrinter::EmitToStreamer for EmitHwasanMemaccessSymbols. (#111792)

2024-10-10 08:43:30 -07:00

i32-icmp.ll

…

i64-icmp.ll

…

iabs.ll

…

idiv_large.ll

…

imm-cse.ll

…

imm.ll

[RISCV] Improve hasAllNBitUsers for users of SLLI.

2024-08-03 18:19:40 -07:00

indirectbr.ll

…

init-array.ll

…

inline-asm-abi-names.ll

…

inline-asm-clobbers.ll

…

inline-asm-d-abi-names.ll

…

inline-asm-d-constraint-f.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-d-modifier-N.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-f-abi-names.ll

…

inline-asm-f-constraint-f.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-f-modifier-N.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-i-constraint-i1.ll

…

inline-asm-invalid.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-mem-constraint-2.ll

[test][RISCV] Precommit inline asm tests for #104925

2024-08-26 13:30:23 +03:00

inline-asm-mem-constraint.ll

[RISCV] Support the large code model. (#70308)

2024-09-09 09:15:07 +08:00

inline-asm-s-constraint-error.ll

…

inline-asm-s-constraint.ll

…

inline-asm-v-constraint.ll

[RISCV] Add support for inline asm constraint vd (#111653)

2024-10-14 10:47:59 +08:00

inline-asm-xsfvcp.ll

[RISCV][VCIX] Add vcix_state to GNU inline assembly register set (#106914)

2024-09-30 23:52:35 -07:00

inline-asm-zdinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm-zfh-constraint-f.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-zfh-modifier-N.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-asm-zfinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm-zhinx-constraint-r.ll

[RISCV] Support inline assembly 'f' constraint for Zfinx. (#112986)

2024-10-18 18:17:23 -07:00

inline-asm.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

inline-option-directive.ll

…

instruction-count-remark.mir

[CodeGen] Fix InstructionCount remarks for MI bundles (#107621)

2024-10-02 13:37:25 -07:00

interrupt-attr-args-error.ll

…

interrupt-attr-callee.ll

…

interrupt-attr-invalid.ll

…

interrupt-attr-nocall.ll

…

interrupt-attr-ret-error.ll

…

interrupt-attr.ll

…

intrinsic-cttz-elts-vscale.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

intrinsic-cttz-elts.ll

…

isel-optnone.ll

…

jumptable-swguarded.ll

[RISCV] Insert simple landing pad for taken address labels. (#91855)

2024-08-06 22:04:48 +08:00

jumptable.ll

…

kcfi-isel-mir.ll

…

kcfi-mir.ll

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

kcfi-patchable-function-prefix.ll

…

kcfi.ll

…

lack-of-signed-truncation-check.ll

[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)

2024-08-04 22:35:38 -07:00

large-stack.ll

…

legalize-fneg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

libcall-tail-calls.ll

…

lit.local.cfg

…

live-sp.mir

…

llvm.exp10.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

llvm.frexp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

load-setcc-combine.ll

…

local-stack-slot-allocation.ll

…

loop-strength-reduce-add-cheaper-than-mul.ll

…

loop-strength-reduce-loop-invar.ll

…

lpad.ll

[RISCV] Insert simple landing pad before indirect jumps for Zicfilp. (#91860)

2024-08-08 13:22:59 +08:00

lsr-legaladdimm.ll

…

machine-combiner-mir.ll

…

machine-combiner-strategies.ll

…

machine-combiner.ll

…

machine-combiner.mir

…

machine-cp.mir

…

machine-cse.ll

…

machine-outliner-and-machine-copy-propagation.ll

…

machine-outliner-cfi.mir

…

machine-outliner-patchable.ll

…

machine-outliner-position.mir

…

machine-outliner-throw.ll

…

machine-sink-load-immediate.ll

[RISCV] Add a testcase for an unprofitable machine-sink issue

2024-09-16 14:17:42 -07:00

machinelicm-address-pseudos.ll

…

machinelicm-constant-phys-reg.ll

…

machineoutliner-jumptable.mir

…

machineoutliner-pcrel-lo.mir

[RISCV] Don't outline pcrel_lo when the function has a section prefix (#107943)

2024-09-11 09:53:11 -07:00

machineoutliner.mir

…

MachineSink-implicit-x0.mir

…

macro-fusion-lui-addi.ll

…

macro-fusions.mir

…

make-compressible-for-store-address.mir

…

make-compressible-rv64.mir

…

make-compressible-zbc-zhinx.mir

[RISCV] Add 16 bit GPR sub-register for Zhinx. (#107446)

2024-09-26 22:56:12 -07:00

make-compressible-zbc.mir

[RISCV] Fix IR for store_large_offset_no_opt_i16 in make-compressible-zbc.mir. NFC

2024-09-16 12:51:07 -07:00

make-compressible-zfinx.mir

[RISCV] Add 32 bit GPR sub-register for Zfinx. (#108336)

2024-10-01 22:09:27 -07:00

make-compressible.mir

…

mem64.ll

…

mem.ll

…

memcpy-inline.ll

…

memcpy.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

memset-inline.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

min-max.ll

…

mir-target-flags.ll

…

misched-load-clustering.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

misched-postra-direction.mir

…

miss-sp-restore-eh.ll

…

module-elf-flags.ll

Reapply "[RISCV] Remove experimental from Ztso. (#96465)"

2024-07-09 10:45:56 -07:00

module-target-abi2.ll

…

module-target-abi3.ll

…

module-target-abi.ll

…

mul.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

musttail-call.ll

…

naked-fn-with-frame-pointer.ll

[llvm] Consistently respect naked fn attribute in TargetFrameLowering::hasFP() (#106014)

2024-10-18 09:35:42 +04:00

narrow-shl-cst.ll

…

neg-abs.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

nest-register.ll

…

nomerge.ll

…

nontemporal-scalable.ll

…

nontemporal.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

O0-pipeline.ll

[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)

2024-09-19 13:39:56 +01:00

O3-pipeline.ll

[RISCV] Add additional fence for amocas when required by recent ABI change (#101023)

2024-09-19 13:39:56 +01:00

opt-w-instrs.mir

…

option-nopic.ll

…

option-norelax.ll

…

option-norvc.ll

…

option-pic.ll

…

option-relax-relocation.ll

…

option-relax.ll

…

option-rvc.ll

…

optnone-store-no-combine.ll

…

or-is-add.ll

…

orc-b-patterns.ll

[RISCV] Re-generate orc-b-patterns.ll for store clustering. NFC

2024-10-11 14:28:51 -07:00

out-of-reach-emergency-slot.mir

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

overflow-intrinsic-optimizations.ll

…

overflow-intrinsics.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

patchable-function-entry.ll

…

pei-crash.ll

…

pic-models.ll

…

pr40333.ll

…

pr51206.ll

…

pr53662.mir

…

pr55201.ll

…

pr56110.ll

…

pr56457.ll

Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)

2024-08-03 01:51:26 +03:00

pr58025.ll

…

pr58286.ll

…

pr58511.ll

…

pr63365.ll

…

pr63816.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

pr64503.ll

…

pr64645.ll

…

pr64772.ll

…

pr64935.ll

…

pr65025.ll

…

pr66603.ll

…

pr68855.ll

…

pr69586.ll

…

pr80052.mir

…

pr84200.ll

…

pr84653_pr85190.ll

[DAGCombiner] Freeze maybe poison operands when folding select to logic (#84924)

2024-07-22 17:19:46 +02:00

pr88365.ll

[LLVM] [MC] Update frame layout & CFI generation to handle frames larger than 2gb (#99263)

2024-07-23 09:43:30 -07:00

pr90652.ll

…

pr90730.ll

…

pr92193.ll

…

pr94145.ll

…

pr94265.ll

[RISCV] Replace hasStdExtV with hasVInstructions in isTruncateFree.

2024-07-29 17:15:02 -07:00

pr95271.ll

Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)

2024-08-03 01:51:26 +03:00

pr95284.ll

[DAG] combineShiftToAVG - don't create avgfloor with scalar constant operands unless legal.

2024-06-13 12:37:43 +01:00

pr96366.ll

[SDAG] Intersect poison-generating flags after CSE (#97434)

2024-07-03 20:32:46 +08:00

pr97304.ll

[RISCV] Add correct MachinePointerInfo when putting arguments on the stack. (#110140)

2024-09-27 13:48:01 -07:00

prefer-w-inst.ll

…

prefer-w-inst.mir

…

prefetch.ll

…

prolog-epilogue.ll

…

push-pop-opt-crash.ll

…

push-pop-popret.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

readcyclecounter.ll

…

readsteadycounter.ll

…

reduce-unnecessary-extension.ll

…

reduction-formation.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

redundant-copy-from-tail-duplicate.ll

[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)

2024-09-10 18:47:20 -07:00

regalloc-last-chance-recoloring-failure.ll

[InitUndef] Enable the InitUndef pass on non-AMDGPU targets (#108353)

2024-09-16 09:48:25 +02:00

relax-per-target-feature.ll

…

rem.ll

…

remat.ll

…

renamable-copy.mir

[TII][RISCV] Add renamable bit to copyPhysReg (#91179)

2024-08-27 10:08:43 +08:00

repeated-fp-divisors.ll

…

reserved-reg-errors.ll

…

reserved-regs.ll

…

riscv-codegen-prepare-atp.ll

[RISCV] Implement RISCVTTIImpl::shouldConsiderAddressTypePromotion for RISCV (#102560)

2024-08-15 10:37:04 +08:00

riscv-codegenprepare-asm.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

riscv-codegenprepare.ll

…

riscv-func-target-feature.ll

…

riscv-shifted-extend.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

riscv-tail-dup-size.ll

[RISCV] Increase default tail duplication threshold to 6 at -O3 (#98873)

2024-08-01 12:24:25 +08:00

rotl-rotr.ll

…

rv32-fuchsia.ll

…

rv32e.ll

…

rv32i-rv64i-float-double.ll

…

rv32i-rv64i-half.ll

…

rv32xtheadba.ll

[RISCV] Strength reduce mul by 2^N - 2^M (#88983)

2024-06-20 07:36:48 -07:00

rv32xtheadbb.ll

[RISCV] Make (sext_inreg X, i1) legal for XTHeadBb to cover the existing isel pattern.

2024-10-11 16:16:07 -07:00

rv32xtheadbs.ll

…

rv32zba.ll

[RISCV] Strength reduce mul by 2^N - 2^M (#88983)

2024-06-20 07:36:48 -07:00

rv32zbb-intrinsic.ll

…

rv32zbb-zbkb.ll

…

rv32zbb.ll

Reland [CodeGenPrepare] Convert ctpop(X) ==/!= 1 into ctpop(X) u</u> 2/1 (#111284) (#111998)

2024-10-15 08:17:50 +08:00

rv32zbc-intrinsic.ll

…

rv32zbc-zbkc-intrinsic.ll

…

rv32zbkb-intrinsic.ll

…

rv32zbkb.ll

[RISCV] Support zext.h mnemonic with Zbkb. (#96821)

2024-06-27 09:31:26 -07:00

rv32zbkx-intrinsic.ll

…

rv32zbs.ll

[RISCV][ISel] Select binvi for pattern icmp eq/ne X, pow2 (#110957)

2024-10-03 15:13:02 +08:00

rv32zimop-intrinsic.ll

…

rv32zknd-intrinsic-autoupgrade.ll

…

rv32zknd-intrinsic.ll

…

rv32zkne-intrinsic-autoupgrade.ll

…

rv32zkne-intrinsic.ll

…

rv32zknh-intrinsic.ll

…

rv32zksed-intrinsic-autoupgrade.ll

…

rv32zksed-intrinsic.ll

…

rv32zksh-intrinsic.ll

…

rv64-large-stack.ll

…

rv64-patchpoint.ll

…

rv64-stackmap-frame-setup.ll

…

rv64-stackmap-nops.ll

…

rv64-stackmap.ll

…

rv64-statepoint-call-lowering-x1.ll

…

rv64-statepoint-call-lowering-x2.ll

…

rv64-statepoint-call-lowering.ll

…

rv64-trampoline.ll

[RISCV] Implement trampolines for rv64 (#96309)

2024-10-18 08:06:47 +02:00

rv64-typepromotion.ll

…

rv64d-double-convert-strict.ll

…

rv64d-double-convert.ll

…

rv64e.ll

…

rv64f-float-convert-strict.ll

…

rv64f-float-convert.ll

…

rv64i-complex-float.ll

…

rv64i-demanded-bits.ll

…

rv64i-double-softfloat.ll

…

rv64i-exhaustive-w-insts.ll

…

rv64i-shift-sext.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

rv64i-single-softfloat.ll

…

rv64i-tricky-shifts.ll

…

rv64i-w-insts-legalization.ll

…

rv64m-exhaustive-w-insts.ll

…

rv64m-w-insts-legalization.ll

…

rv64xtheadba.ll

[RISCV] Strength reduce mul by 2^N - 2^M (#88983)

2024-06-20 07:36:48 -07:00

rv64xtheadbb.ll

[RISCV] Make (sext_inreg X, i1) legal for XTHeadBb to cover the existing isel pattern.

2024-10-11 16:16:07 -07:00

rv64xtheadbs.ll

…

rv64zba.ll

[RISCV][ISel] Allow emitting addiw with u32simm12 rhs (#111116)

2024-10-05 09:23:29 +08:00

rv64zbb-intrinsic.ll

…

rv64zbb-zbkb.ll

…

rv64zbb.ll

Reland [CodeGenPrepare] Convert ctpop(X) ==/!= 1 into ctpop(X) u</u> 2/1 (#111284) (#111998)

2024-10-15 08:17:50 +08:00

rv64zbc-intrinsic.ll

…

rv64zbc-zbkc-intrinsic.ll

…

rv64zbkb-intrinsic.ll

…

rv64zbkb.ll

[RISCV] Support zext.h mnemonic with Zbkb. (#96821)

2024-06-27 09:31:26 -07:00

rv64zbkx-intrinsic.ll

…

rv64zbs.ll

[RISCV][DAGCombine] Combine sext_inreg (shl X, Y), i32 into sllw X, Y (#111101)

2024-10-04 16:03:09 +08:00

rv64zfh-half-convert-strict.ll

…

rv64zfh-half-convert.ll

[RISCV] Don't combine (sext_inreg (fmv_x_anyexth X), i16) with Zhinx.

2024-08-14 15:18:10 -07:00

rv64zfh-half-intrinsics.ll

…

rv64zfhmin-half-convert-strict.ll

[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)

2024-09-03 13:33:14 -07:00

rv64zfhmin-half-convert.ll

[RISCV] Custom promote f16/bf16 (s/u)int_to_fp. (#107026)

2024-09-03 13:33:14 -07:00

rv64zfhmin-half-intrinsics.ll

…

rv64zimop-intrinsic.ll

…

rv64zknd-intrinsic.ll

…

rv64zknd-zkne-intrinsic.ll

…

rv64zkne-intrinsic.ll

…

rv64zknh-intrinsic-autoupgrade.ll

…

rv64zknh-intrinsic.ll

…

rv64zksed-intrinsic-autoupgrade2.ll

…

rv64zksed-intrinsic-autoupgrade.ll

…

rv64zksed-intrinsic.ll

…

rv64zksh-intrinsic-autoupgrade.ll

…

rv64zksh-intrinsic.ll

…

rvv-cfi-info.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

sadd_sat_plus.ll

…

sadd_sat.ll

…

saverestore-scs.ll

…

saverestore.ll

…

scmp.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

sdata-limit-0.ll

…

sdata-limit-4.ll

…

sdata-limit-8.ll

…

sdata-local-sym.ll

…

sdata-sections.ll

[RISCV] Let -data-sections also work on sbss/sdata sections (#87040)

2024-08-23 14:06:12 +01:00

sdiv-pow2-cmov.ll

…

select-and.ll

…

select-bare.ll

…

select-binop-identity.ll

…

select-cc.ll

…

select-const.ll

…

select-constant-xor.ll

…

select-optimize-multiple.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

select-optimize-multiple.mir

…

select-or.ll

…

select-to-and-zext.ll

…

select.ll

[RISCV] Add coverage for select C, C1, C2 where (C1-C2)*[0,1] is cheap

2024-09-16 12:46:43 -07:00

selectcc-to-shiftand.ll

[RISCV] Limit (and (sra x, c2), c1) -> (srli (srai x, c2-c3), c3) isel in some cases. (#102034)

2024-08-06 20:27:14 -07:00

setcc-logic.ll

…

sext-zext-trunc.ll

…

sextw-removal-debug.mir

…

sextw-removal.ll

Revert "[SDag][ARM][RISCV] Allow lowering CTPOP into a libcall" (#101740)

2024-08-03 01:51:26 +03:00

shadowcallstack.ll

…

shift-amount-mod.ll

…

shift-and.ll

…

shift-masked-shamt.ll

…

shifts.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

shl-cttz.ll

[RISCV] Remove riscv-experimental-rv64-legal-i32. (#102509)

2024-08-09 11:48:48 -07:00

shl-demanded.ll

…

shlimm-addimm.ll

…

short-forward-branch-opt.ll

…

shrinkwrap-jump-table.ll

…

shrinkwrap.ll

…

sifive7-enable-intervals.mir

…

signbit-test.ll

…

signed-truncation-check.ll

[RISCV] Select (and (sra x, c2), c1) as (srli (srai x, c2-c3), c3). (#101868)

2024-08-04 22:35:38 -07:00

sink-and-fold-crash.mir

[MachineSink][RISCV] Only call isConstantPhysReg or isIgnorableUse for uses. (#99363)

2024-07-17 13:06:58 -07:00

sink-icmp.ll

…

spill-fill-fold.ll

…

spill-fpr-scalar.ll

…

spir-kernel-cc.ll

…

split-offsets.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

split-sp-adjust.ll

…

split-store.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

split-udiv-by-constant.ll

…

split-urem-by-constant.ll

…

srem-lkk.ll

…

srem-seteq-illegal-types.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

srem-vector-lkk.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

srodata.ll

…

ssub_sat_plus.ll

…

ssub_sat.ll

…

stack-folding.ll

…

stack-guard-global.ll

[RISCV] Support -mstack-protector-guard=tls (#108942)

2024-10-02 16:33:31 -07:00

stack-guard-tls.ll

[RISCV] Support -mstack-protector-guard=tls (#108942)

2024-10-02 16:33:31 -07:00

stack-inst-compress.mir

…

stack-offset.ll

…

stack-protector-target.ll

…

stack-realignment-with-variable-sized-objects.ll

…

stack-realignment.ll

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

stack-slot-coloring.mir

…

stack-slot-size.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

stack-store-check.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

subtarget-features-std-ext.ll

…

switch-width.ll

…

tagged-globals.ll

…

tail-calls.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

target-abi-invalid.ll

…

target-abi-valid.ll

…

thread-pointer.ll

…

tls-models.ll

…

tlsdesc-symbol.ll

…

trunc-free.ll

…

typepromotion-overflow.ll

…

uadd_sat_plus.ll

[LegalizeTypes][RISCV] Use signed promotion for UADDSAT if that's what the target prefers. (#102842)

2024-08-12 09:34:51 -07:00

uadd_sat.ll

…

ucmp.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

umulo-128-legalisation-lowering.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

unaligned-load-store.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

unfold-masked-merge-scalar-variablemask.ll

…

unroll-loop-cse.ll

…

urem-lkk.ll

…

urem-seteq-illegal-types.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

urem-vector-lkk.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

usub_sat_plus.ll

[LegalizeTypes][RISCV] Use SExtOrZExtPromotedOperands to promote operands for USUBSAT. (#102781)

2024-08-11 10:22:31 -07:00

usub_sat.ll

…

vararg-ilp32e.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vararg.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vector-abi.ll

…

verify-instr.mir

[CodeGen][NewPM] Port MachineVerifier to new pass manager (#98628)

2024-07-15 12:42:44 +08:00

vlenb.ll

…

vscale-demanded-bits.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

wide-mem.ll

…

wide-scalar-shift-by-byte-multiple-legalization.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

wide-scalar-shift-legalization.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

xaluo.ll

…

xcvalu.ll

[RISCV] Implement Clang Builtins for XCValu Extension in CV32E40P (#100684)

2024-10-01 11:22:02 +10:00

xcvbi.ll

…

xcvbitmanip.ll

…

xcvmac.ll

[RISCV] Implement Intrinsics for XCVmac Extension in CV32E40P (#83112)

2024-07-15 10:25:25 +10:00

xcvmem.ll

[RISCV] Codegen support for XCVmem extension (#76916)

2024-06-07 21:45:49 +08:00

xtheadfmemidx.ll

…

xtheadmac.ll

…

xtheadmemidx.ll

…

xtheadmempair.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

zbb-cmp-combine.ll

…

zcb-regalloc-hints.ll

…

zcmp-additional-stack.ll

…

zcmp-cm-popretz.mir

…

zcmp-cm-push-pop.mir

…

zcmp-prolog-epilog-crash.mir

…

zcmp-with-float.ll

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zdinx-asm-constraint.ll

[RISCV] Inline Assembly: RVC constraint and N modifier (#112561)

2024-10-18 10:40:38 +01:00

zdinx-boundary-check.ll

[RISCV] Fix another RV32 Zdinx load/store addressing corner case.

2024-09-04 23:26:40 -07:00

zdinx-large-spill.mir

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zext-with-load-is-free.ll

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zfh-half-intrinsics-strict.ll

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zfh-half-intrinsics.ll

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zfhmin-half-intrinsics-strict.ll

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zfhmin-half-intrinsics.ll

[RISCV] Add test for llvm.round.i32.f16 RV64+Zfhmin/Zhinxmin. NFC

2024-09-01 12:15:00 -07:00

zfhmin-imm.ll

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zicfilp-indirect-branch.ll

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zmmul.ll

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