228f88fdc8
This change implements support for the `cr` and `cf` register constraints (which allocate a RVC GPR or RVC FPR respectively), and the `N` modifier (which prints the raw encoding of a register rather than the name). The intention behind these additions is to make it easier to use inline assembly when assembling raw instructions that are not supported by the compiler, for instance when experimenting with new instructions or when supporting proprietary extensions outside the toolchain. These implement part of my proposal in riscv-non-isa/riscv-c-api-doc#92 As part of the implementation, I felt there was not enough coverage of inline assembly and the "in X" floating-point extensions, so I have added more regression tests around these configurations.
110 lines
3.8 KiB
LLVM
110 lines
3.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -target-abi=ilp32 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV32F %s
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; RUN: llc -mtriple=riscv64 -mattr=+d -target-abi=lp64 -verify-machineinstrs -no-integrated-as < %s \
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; RUN: | FileCheck -check-prefix=RV64F %s
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;; `.insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)` is
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;; the raw encoding for `fadd.d`
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@gd = external global double
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define double @constraint_f_double(double %a) nounwind {
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; RV32F-LABEL: constraint_f_double:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -16
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld fa5, 8(sp)
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; RV32F-NEXT: lui a0, %hi(gd)
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; RV32F-NEXT: fld fa4, %lo(gd)(a0)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fsd fa5, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 16
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_double:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gd)
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; RV64F-NEXT: fld fa5, %lo(gd)(a1)
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; RV64F-NEXT: fmv.d.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.d a0, fa5
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; RV64F-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=f,f,f"(double %a, double %1)
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ret double %2
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}
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define double @constraint_cf_double(double %a) nounwind {
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; RV32F-LABEL: constraint_cf_double:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -16
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld fa5, 8(sp)
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; RV32F-NEXT: lui a0, %hi(gd)
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; RV32F-NEXT: fld fa4, %lo(gd)(a0)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (15 << 15) | (14 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fsd fa5, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 16
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_cf_double:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gd)
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; RV64F-NEXT: fld fa5, %lo(gd)(a1)
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; RV64F-NEXT: fmv.d.x fa4, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x02000053 | (15 << 7) | (14 << 15) | (15 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.d a0, fa5
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; RV64F-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "=^cf,^cf,^cf"(double %a, double %1)
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ret double %2
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}
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define double @constraint_f_double_abi_name(double %a) nounwind {
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; RV32F-LABEL: constraint_f_double_abi_name:
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; RV32F: # %bb.0:
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; RV32F-NEXT: addi sp, sp, -16
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; RV32F-NEXT: sw a0, 8(sp)
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; RV32F-NEXT: sw a1, 12(sp)
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; RV32F-NEXT: fld fa1, 8(sp)
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; RV32F-NEXT: lui a0, %hi(gd)
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; RV32F-NEXT: fld fs0, %lo(gd)(a0)
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; RV32F-NEXT: #APP
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; RV32F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20)
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; RV32F-NEXT: #NO_APP
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; RV32F-NEXT: fsd ft0, 8(sp)
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; RV32F-NEXT: lw a0, 8(sp)
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; RV32F-NEXT: lw a1, 12(sp)
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; RV32F-NEXT: addi sp, sp, 16
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; RV32F-NEXT: ret
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;
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; RV64F-LABEL: constraint_f_double_abi_name:
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; RV64F: # %bb.0:
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; RV64F-NEXT: lui a1, %hi(gd)
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; RV64F-NEXT: fld fs0, %lo(gd)(a1)
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; RV64F-NEXT: fmv.d.x fa1, a0
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; RV64F-NEXT: #APP
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; RV64F-NEXT: .insn 0x4, 0x02000053 | (0 << 7) | (11 << 15) | (8 << 20)
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; RV64F-NEXT: #NO_APP
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; RV64F-NEXT: fmv.x.d a0, ft0
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; RV64F-NEXT: ret
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%1 = load double, ptr @gd
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%2 = tail call double asm ".insn 0x4, 0x02000053 | (${0:N} << 7) | (${1:N} << 15) | (${2:N} << 20)", "={ft0},{fa1},{fs0}"(double %a, double %1)
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ret double %2
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}
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