Harald van Dijk 950ee75909 [RISC-V] Fix check of minimum vlen. (#114055) ...

If we have a minimum vlen, we were adjusting StackSize to change the
unit from vscale to bytes, and then calculating the required padding
size for alignment in bytes. However, we then used that padding size as
an offset in vscale units, resulting in misplaced stack objects.

While it would be possible to adjust the object offsets by dividing
AlignmentPadding by ST.getRealMinVLen() / RISCV::RVVBitsPerBlock, we can
simplify the calculation a bit if instead we adjust the alignment to be
in vscale units.

@topperc This fixes a bug I am seeing after #110312, but I am not 100%
certain I am understanding the code correctly, could you please see if
this makes sense to you?

2024-10-29 17:30:30 +00:00

..

65704-illegal-instruction.ll

[MachineLICM] Hoist copies of constant physical register (#93285)

2024-05-29 14:10:01 +08:00

abd.ll

[DAG] Add legalization handling for ABDS/ABDU (#92576) (REAPPLIED)

2024-08-08 11:39:05 +01:00

abs-sdnode.ll

…

abs-vp.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

access-fixed-objects-by-rvv.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

active_lane_mask.ll

[RISCV] Add a rematerializable pseudo instruction for LUI+ADDI for global addresses. (#93352)

2024-05-28 15:05:23 -07:00

addi-rvv-stack-object.mir

…

addi-scalable-offset.mir

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

aliases.mir

…

alloca-load-store-scalable-array.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

alloca-load-store-scalable-struct.ll

…

alloca-load-store-vector-tuple.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

allocate-lmul-2-4-8.ll

[RISC-V] Fix check of minimum vlen. (#114055)

2024-10-29 17:30:30 +00:00

allone-masked-to-unmasked.ll

…

binop-splats.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

binop-zext.ll

…

bitreverse-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

bitreverse-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

bswap-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

bswap-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

callee-saved-regs.ll

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

calling-conv-fastcc.ll

[RISCV] Support fastcc passing scalable vectors indirectly with no free GPRs. (#107623)

2024-09-06 17:10:01 -07:00

calling-conv.ll

[RISCV] Update vector calling convention test for tuple type. NFC (#111336)

2024-10-08 08:25:47 -07:00

ceil-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

cmp-folds.ll

…

combine-sats.ll

…

combine-splats.ll

…

combine-store-extract-crash.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

combine-store.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

common-shuffle-patterns.ll

…

commutable.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

commuted-op-indices-regression.mir

…

compressstore.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

concat-vector-insert-elt.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

concat-vectors-constant-stride.ll

[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440)

2024-05-15 11:44:32 +08:00

constant-folding-crash.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

constant-folding.ll

…

copyprop.mir

[RISCV] Rename vcix_state register to sf_vcix_state. NFC (#106995)

2024-09-03 15:55:39 +08:00

cross-block-cse.ll

…

ctlz-sdnode.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

ctlz-vp.ll

[DAGCombine] Count leading ones: refine post DAG/Type Legalisation if promotion (#102877)

2024-09-15 15:48:36 +04:00

ctpop-sdnode.ll

…

ctpop-vp.ll

[RISCV] Rematerialize vmv.v.x (#107993)

2024-09-11 09:13:23 +08:00

cttz-sdnode.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

cttz-vp.ll

[RISCV] Rematerialize vmv.v.x (#107993)

2024-09-11 09:13:23 +08:00

debug-info-rvv-dbg-value.mir

…

dont-sink-splat-operands.ll

Revert "[RISCV] Enable TTI::shouldDropLSRSolutionIfLessProfitable by default" (#98328)

2024-07-10 15:33:20 +01:00

double-round-conv.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

emergency-slot.mir

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

expand-no-v.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

extload-truncstore.ll

…

extract-subvector.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

extractelt-fp.ll

[RISCV] Handle f16/bf16 extract_vector_elt when scalar type is legal (#110144)

2024-09-27 08:00:59 +08:00

extractelt-i1.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

extractelt-int-rv32.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

extractelt-int-rv64.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fceil-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fceil-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

ffloor-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

ffloor-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fixed-vector-i8-index-cornercase.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

fixed-vectors-abd.ll

…

fixed-vectors-abs-vp.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-abs.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

fixed-vectors-binop-splats.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-bitcast-large-vector.ll

…

fixed-vectors-bitcast.ll

[RISCV] Remove vfmv.s.f and vfmv.f.s lmul pseudo variants (#100970)

2024-07-29 22:01:17 +08:00

fixed-vectors-bitreverse-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-bitreverse.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-bswap-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-bswap.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-buildvec-of-binop.ll

[CodeGen] Clear InitUndef pass new register cache between pass runs (#90967)

2024-09-12 15:01:55 +02:00

fixed-vectors-calling-conv-fastcc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-calling-conv.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-ceil-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-compress-fp.ll

[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770)

2024-10-28 09:37:06 +00:00

fixed-vectors-compress-int.ll

[RISCV] Add lowering for @llvm.experimental.vector.compress (#113291)

2024-10-23 14:22:32 +08:00

fixed-vectors-compressstore-fp.ll

…

fixed-vectors-compressstore-int.ll

…

fixed-vectors-ctlz-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-ctlz.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

fixed-vectors-ctpop-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-ctpop.ll

…

fixed-vectors-cttz-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-cttz.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

fixed-vectors-deinterleave-load.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-elen.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-emergency-slot.mir

…

fixed-vectors-expandload-fp.ll

[RISCV][InsertVSETVLI] Eliminate the AVLIsIgnored state (#94658)

2024-06-17 08:20:37 -07:00

fixed-vectors-expandload-int.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-extload-truncstore.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-extract-i1.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-extract-subvector.ll

[RISCV] Unify getDemanded between forward and backwards passes in RISCVInsertVSETVLI (#92860)

2024-05-21 14:11:42 +08:00

fixed-vectors-extract.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fceil-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-ffloor-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-floor-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fmaximum-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fmaximum.ll

…

fixed-vectors-fmf.ll

…

fixed-vectors-fminimum-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fminimum.ll

…

fixed-vectors-fnearbyint-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-fp2i-sat.ll

[RISCV] Use vnclip(u) to handle fp_to_(s/u)int_sat that needs additional narrowing. (#100071)

2024-07-23 09:09:35 -07:00

fixed-vectors-fp2i.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-fp-bitcast.ll

[RISCV] Remove vfmv.s.f and vfmv.f.s lmul pseudo variants (#100970)

2024-07-29 22:01:17 +08:00

fixed-vectors-fp-buildvec-bf16.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fixed-vectors-fp-buildvec.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-fp-conv.ll

…

fixed-vectors-fp-interleave.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fp-setcc.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-fp-shuffles.ll

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205)

2024-07-10 07:35:56 -07:00

fixed-vectors-fp-splat-bf16.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-fp-splat.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-fp-vrgather.ll

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205)

2024-07-10 07:35:56 -07:00

fixed-vectors-fp.ll

[RISCV] Promote fixed-length bf16 arith vector ops with zvfbfmin (#112393)

2024-10-15 22:49:05 +01:00

fixed-vectors-fpext-vp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-fptosi-vp-mask.ll

…

fixed-vectors-fptosi-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fptoui-vp-mask.ll

…

fixed-vectors-fptoui-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-fptrunc-vp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-fround-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-fround.ll

…

fixed-vectors-froundeven-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-froundeven.ll

…

fixed-vectors-fshr-fshl-vp.ll

…

fixed-vectors-ftrunc-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fixed-vectors-i2fp.ll

[RISCV] Remove {s,u}int_to_fp custom op action for f16/bf16 (#111471)

2024-10-10 14:40:24 +01:00

fixed-vectors-insert-i1.ll

…

fixed-vectors-insert-subvector-shuffle.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

fixed-vectors-insert-subvector.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-insert.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-int-buildvec.ll

[RISCV] Coverage for a few missed vector idioms

2024-10-25 16:28:36 -07:00

fixed-vectors-int-explodevector.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-int-exttrunc.ll

…

fixed-vectors-int-interleave.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-int-setcc.ll

…

fixed-vectors-int-shuffles.ll

[RISCV] Reorder shuffle operands if one side is an identity (#98534)

2024-07-11 13:52:41 -07:00

fixed-vectors-int-splat.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-int-vrgather.ll

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205)

2024-07-10 07:35:56 -07:00

fixed-vectors-int.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-interleave-store.ll

…

fixed-vectors-interleaved-access-zve32x.ll

[RISCV] Enable load clustering by default (#73789)

2024-10-01 13:45:30 +01:00

fixed-vectors-interleaved-access.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fixed-vectors-inttoptr-ptrtoint.ll

…

fixed-vectors-llrint-vp.ll

…

fixed-vectors-llrint.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-load-store.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-load.ll

[RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (#107297)

2024-09-04 17:49:50 -07:00

fixed-vectors-lrint-vp.ll

…

fixed-vectors-lrint.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-marith-vp.ll

…

fixed-vectors-mask-buildvec.ll

[RISCV] Coverage for a few missed vector idioms

2024-10-25 16:28:36 -07:00

fixed-vectors-mask-load-store.ll

…

fixed-vectors-mask-logic.ll

…

fixed-vectors-mask-splat.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-masked-gather.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-masked-load-fp.ll

…

fixed-vectors-masked-load-int.ll

[LegalizeTypes][RISCV] Use SPLAT_VECTOR_PARTS to legalize splat BUILD_VECTOR (#107290)

2024-09-04 19:14:18 -07:00

fixed-vectors-masked-scatter.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-masked-store-fp.ll

…

fixed-vectors-masked-store-int.ll

[LegalizeTypes][RISCV] Use SPLAT_VECTOR_PARTS to legalize splat BUILD_VECTOR (#107290)

2024-09-04 19:14:18 -07:00

fixed-vectors-nearbyint-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-non-power-of-2.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

fixed-vectors-peephole-vmerge-vops.ll

…

fixed-vectors-reduction-formation.ll

[RISCV] Add reductions to list of roots in tryToReduceVL (#107595)

2024-09-10 18:47:20 -07:00

fixed-vectors-reduction-fp-vp.ll

[SDAG][RISCV] Don't promote VP_REDUCE_{FADD,FMUL} (#111000)

2024-10-04 00:17:45 +08:00

fixed-vectors-reduction-fp.ll

[DAG] Prefer 0.0 over -0.0 as neutral value for FADD w/NoSignedZero (#106616)

2024-08-30 07:56:14 -07:00

fixed-vectors-reduction-int-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-reduction-int.ll

[DAG][RISCV] Use vp_reduce_* when widening illegal types for reductions (#105455)

2024-08-22 07:30:39 -07:00

fixed-vectors-reduction-mask-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-rint-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-round-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-roundeven-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-roundtozero-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-sad.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-segN-load.ll

…

fixed-vectors-segN-store.ll

…

fixed-vectors-select-bf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-select-fp.ll

[RISCV] Add back some test cases I inadvertently deleted. NFC

2024-06-24 10:01:52 -07:00

fixed-vectors-select-int.ll

…

fixed-vectors-setcc-fp-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-setcc-int-vp-mask.ll

…

fixed-vectors-setcc-int-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-sext-vp-mask.ll

…

fixed-vectors-sext-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-shuffle-concat.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-shuffle-exact-vlen.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-shuffle-extract-subvector.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

fixed-vectors-shuffle-reverse.ll

[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (#104574)

2024-08-29 14:32:41 +08:00

fixed-vectors-shuffle-rotate.ll

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00

fixed-vectors-shuffle-transpose.ll

[RISCV] Reorder shuffle operands if one side is an identity (#98534)

2024-07-11 13:52:41 -07:00

fixed-vectors-shuffle-vslide1down.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-shuffle-vslide1up.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-shufflevector-vnsrl.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-sitofp-vp-mask.ll

…

fixed-vectors-sitofp-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-stepvector.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

fixed-vectors-store-merge-crash.ll

…

fixed-vectors-store.ll

[RISCV] Support fixed vector VP_LOAD/STORE for bf16 and f16 without Zvfh. (#107297)

2024-09-04 17:49:50 -07:00

fixed-vectors-strided-load-combine.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

fixed-vectors-strided-load-store-asm.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-strided-load-store-negative.ll

…

fixed-vectors-strided-load-store.ll

[RISCV] Emit VP strided loads/stores in RISCVGatherScatterLowering (#98111)

2024-07-24 13:56:22 +08:00

fixed-vectors-strided-vpload.ll

[RISCV] Use experimental.vp.splat to splat specific vector length elements. (#101329)

2024-08-01 09:37:42 +08:00

fixed-vectors-strided-vpstore.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-trunc-sat-clip.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468)

2024-08-16 08:42:36 -07:00

fixed-vectors-trunc-vp-mask.ll

…

fixed-vectors-trunc-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-uitofp-vp-mask.ll

…

fixed-vectors-uitofp-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-unaligned.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vaaddu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vadd-vp-mask.ll

…

fixed-vectors-vadd-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vand-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vcopysign-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vdiv-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vdivu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vfabs-vp.ll

[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)

2024-08-30 09:44:51 -07:00

fixed-vectors-vfadd-constrained-sdnode.ll

…

fixed-vectors-vfadd-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfclass-vp.ll

…

fixed-vectors-vfclass.ll

…

fixed-vectors-vfcmp-constrained-sdnode.ll

…

fixed-vectors-vfcmps-constrained-sdnode.ll

…

fixed-vectors-vfdiv-constrained-sdnode.ll

…

fixed-vectors-vfdiv-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfma-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmacc-vp.ll

…

fixed-vectors-vfmadd-constrained-sdnode.ll

…

fixed-vectors-vfmax-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vfmax.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmin-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vfmin.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmsac-vp.ll

…

fixed-vectors-vfmsub-constrained-sdnode.ll

…

fixed-vectors-vfmul-constrained-sdnode.ll

…

fixed-vectors-vfmul-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfmuladd-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vfneg-vp.ll

[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)

2024-08-30 09:44:51 -07:00

fixed-vectors-vfnmacc-vp.ll

…

fixed-vectors-vfnmadd-constrained-sdnode.ll

…

fixed-vectors-vfnmsac-vp.ll

…

fixed-vectors-vfnmsub-constrained-sdnode.ll

…

fixed-vectors-vfpext-constrained-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-vfptoi-constrained-sdnode.ll

[RISCV] Custom promote f16/bf16 fp_to_(s/u)int to reduce isel patterns that emit two instructions. (#107011)

2024-09-03 15:34:25 -07:00

fixed-vectors-vfptrunc-constrained-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

fixed-vectors-vfrdiv-vp.ll

…

fixed-vectors-vfrsub-vp.ll

…

fixed-vectors-vfsqrt-constrained-sdnode.ll

…

fixed-vectors-vfsqrt-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vfsub-constrained-sdnode.ll

…

fixed-vectors-vfsub-vp.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vfw-web-simplification.ll

[RISCV] Add FMA support to combineOp_VLToVWOp_VL. (#100454)

2024-07-26 09:12:40 -07:00

fixed-vectors-vfwadd.ll

[RISCV] Form VFWMUL.VF and VFWADD.VF/WF when fp_extend is scalar and then splatted. (#98590)

2024-07-15 17:50:23 -07:00

fixed-vectors-vfwmacc.ll

[RISCV] Add FMA support to combineOp_VLToVWOp_VL. (#100454)

2024-07-26 09:12:40 -07:00

fixed-vectors-vfwmaccbf16.ll

[ValueTypes][RISCV] Add v1bf16 type (#111112)

2024-10-06 22:20:51 +08:00

fixed-vectors-vfwmul.ll

[RISCV] Form VFWMUL.VF and VFWADD.VF/WF when fp_extend is scalar and then splatted. (#98590)

2024-07-15 17:50:23 -07:00

fixed-vectors-vfwsub.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vitofp-constrained-sdnode.ll

…

fixed-vectors-vmacc-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vmax-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vmaxu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vmin-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vminu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vmul-vp-mask.ll

…

fixed-vectors-vmul-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vnmsac-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vnsra-vnsrl.ll

…

fixed-vectors-vor-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vp-splat.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vpgather.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vpload.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vpmerge-bf16.ll

[RISCV] Bitcast fixed length bf16/f16 build_vector to i16 with Zvfbfmin/Zvfhmin+Zfbfmin/Zfhmin. (#106637)

2024-09-03 17:50:04 -07:00

fixed-vectors-vpmerge.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vpscatter.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fixed-vectors-vpstore.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vreductions-mask.ll

…

fixed-vectors-vrem-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vremu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vrol.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

fixed-vectors-vror.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

fixed-vectors-vrsub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vsadd-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vsadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vsaddu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vsaddu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vscale-range.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vselect-vp-bf16.ll

[RISCV] Remove Zfbfmin from some vector test RUN lines. NFC

2024-07-31 22:25:23 -07:00

fixed-vectors-vselect-vp.ll

[RISCV] Remove duplicate bf16 testing. NFC

2024-06-13 20:05:24 -07:00

fixed-vectors-vselect.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

fixed-vectors-vshl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

fixed-vectors-vsra-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

fixed-vectors-vsrl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

fixed-vectors-vssub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vssub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vssubu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vssubu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vsub-vp-mask.ll

…

fixed-vectors-vsub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vw-web-simplification.ll

…

fixed-vectors-vwadd-mask.ll

…

fixed-vectors-vwadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vwaddu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vwmacc.ll

…

fixed-vectors-vwmaccsu.ll

…

fixed-vectors-vwmaccu.ll

…

fixed-vectors-vwmaccus.ll

…

fixed-vectors-vwmul.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vwmulsu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vwmulu.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

fixed-vectors-vwsll.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

fixed-vectors-vwsub-mask.ll

…

fixed-vectors-vwsub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vwsubu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-vxor-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fixed-vectors-xsfvcp-x.ll

…

fixed-vectors-xsfvcp-xv.ll

…

fixed-vectors-xsfvcp-xvv.ll

[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630)

2024-10-14 21:10:55 -07:00

fixed-vectors-xsfvcp-xvw.ll

…

fixed-vectors-zext-vp-mask.ll

…

fixed-vectors-zext-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

float-round-conv.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

floor-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fmaximum-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fmaximum-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fminimum-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fminimum-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fnearbyint-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fnearbyint-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fold-binary-reduce.ll

[RISCV] Coverage for a few missed vector idioms

2024-10-25 16:28:36 -07:00

fold-binop-into-select.ll

…

fold-scalar-load-crash.ll

[MachineLICM] Hoist copies of constant physical register (#93285)

2024-05-29 14:10:01 +08:00

fold-vector-cmp.ll

…

fold-vp-fadd-and-vp-fmul.ll

…

fold-vp-fsub-and-vp-fmul.ll

…

fpclamptosat_vec.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

fptosi-sat.ll

[RISCV] Use vnclip(u) to handle fp_to_(s/u)int_sat that needs additional narrowing. (#100071)

2024-07-23 09:09:35 -07:00

fptoui-sat.ll

[RISCV] Use vnclip(u) to handle fp_to_(s/u)int_sat that needs additional narrowing. (#100071)

2024-07-23 09:09:35 -07:00

frameindex-addr.ll

…

frint-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

frm-insert.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

fround-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

fround-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

froundeven-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

froundeven-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

fshr-fshl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

fshr-fshl.ll

…

ftrunc-constrained-sdnode.ll

[RISCV] Use mask undisturbed policy when silencing sNans for strict rounding ops. (#93356)

2024-05-28 08:51:42 -07:00

ftrunc-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

get_vector_length.ll

…

get-vlen-debugloc.mir

…

half-round-conv.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

handle-noreg-with-implicit-def.mir

[CodeGen] Add generic INIT_UNDEF pseudo (#106744)

2024-09-05 09:34:39 +02:00

implicit-def-copy.ll

…

inline-asm.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

insert-subvector.ll

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00

insertelt-fp.ll

[RISCV] Move bfloat tests back above half. NFC

2024-10-02 15:30:49 +08:00

insertelt-i1.ll

…

insertelt-int-rv32.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

insertelt-int-rv64.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

interleave-crash.ll

…

known-never-zero.ll

[SelectionDAG] Handle VSCALE in isKnownNeverZero (#97789)

2024-07-05 16:11:06 +08:00

large-rvv-stack-size.mir

[RISCV] fix SP recovery in a function epilogue (#110809)

2024-10-04 12:22:11 +03:00

legalize-load-sdnode.ll

…

legalize-scalable-vectortype.ll

…

legalize-store-sdnode.ll

[RISCV] Remove unncessary FP extensions from some integer only vector tests.

2024-07-31 15:21:03 -07:00

llrint-sdnode.ll

…

llrint-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

load-add-store.ll

…

load-bf16.ll

[RISCV] Expand bf16 vector truncstores and extloads (#108235)

2024-09-12 08:42:25 +08:00

load-mask.ll

…

localvar.ll

…

lrint-sdnode.ll

…

lrint-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

marith-vp.ll

…

mask-exts-truncs.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

mask-reg-alloc.mir

[RISCV] Change more undef passthrus to $noreg in vector tests. NFC

2024-05-07 16:02:18 +08:00

masked-load-fp.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

masked-load-int.ll

…

masked-store-fp.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

masked-store-int.ll

…

masked-tama.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

masked-tamu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

masked-tuma.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

masked-tumu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

masked-vslide1down-rv32.ll

…

memcpy-crash-zvl32b.ll

[RISCV] Disable fixed vectors in getOptimalMemOpType if minimum VLEN is 32. (#102974)

2024-08-12 20:55:13 -07:00

memcpy-inline.ll

…

memory-args.ll

…

memset-inline.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

mgather-sdnode.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

mscatter-combine.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

mscatter-sdnode.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

mul-combine.ll

[RISCV] Combine vXi32 (mul (and (lshr X, 15), 0x10001), 0xffff) -> (bitcast (sra (v2Xi16 (bitcast X)), 15)) (#93565)

2024-05-28 15:54:44 -07:00

mutate-prior-vsetvli-avl.ll

…

named-vector-shuffle-reverse.ll

[RISCV] Lower vector_reverse for zvfhmin/zvfbfmin (#110218)

2024-10-02 14:25:15 +08:00

narrow-shift-extend.ll

…

nearbyint-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

no-reserved-frame.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

pass-fast-math-flags-sdnode.ll

…

pr52475.ll

…

pr61561.ll

…

pr63459.ll

…

pr63596.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

pr64588.ll

…

pr83017.ll

[RISCV] Move exact VLEN VLMAX transform to RISCVVectorPeephole (#100551)

2024-07-26 07:56:12 +08:00

pr83920.ll

…

pr88576.ll

…

pr88799.ll

…

pr90559.ll

[RISCV] Move exact VLEN VLMAX transform to RISCVVectorPeephole (#100551)

2024-07-26 07:56:12 +08:00

pr93587.ll

[RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals

2024-06-17 12:05:43 -07:00

pr95865.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

pr99782.ll

[RISCV] Update test for #99821 after #100116. NFC

2024-07-24 12:10:45 +08:00

pr104480.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

pr106109.ll

[RISCV] Fix v[f]slide1down.vx having VL changed (#106110)

2024-08-29 12:50:12 +08:00

pr107950.ll

[RISCV] Mark pointer masking extensions as non-experimental (#113618)

2024-10-25 12:24:50 +01:00

reduce-vl-peephole.ll

[RISCV] Check VL dominates and potentially move in tryReduceVL (#106753)

2024-08-31 01:50:24 +08:00

reduce-vl-peephole.mir

[RISCV] Check VL dominates and potentially move in tryReduceVL (#106753)

2024-08-31 01:50:24 +08:00

reg-alloc-reserve-bp.ll

…

reg-coalescing.mir

…

regalloc-fast-crash.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

remat.ll

[RISCV] Remove support for pre-RA vsetvli insertion (#110796)

2024-10-28 11:31:18 +00:00

rint-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

riscv-codegenprepare-asm.ll

…

riscv-codegenprepare.ll

…

round-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

roundeven-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

roundtozero-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

rv32-spill-vector-csr.ll

[RISCV] Remove unnecessary patterns for tail agnostic FP intrinsics with rounding mode. (#94498)

2024-06-05 13:11:28 -05:00

rv32-spill-vector.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

rv32-spill-zvlsseg.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

rv64-spill-vector-csr.ll

[RISCV] Remove unnecessary patterns for tail agnostic FP intrinsics with rounding mode. (#94498)

2024-06-05 13:11:28 -05:00

rv64-spill-vector.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

rv64-spill-zvlsseg.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

rvv-args-by-mem.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

rvv-framelayout.ll

…

rvv-out-arguments.ll

[RISCV] Add unit strided load/store to whole register peephole (#100116)

2024-07-24 11:52:54 +08:00

rvv-peephole-vmerge-masked-vops.ll

[RISCV] Reduce VL of vmerge.vvm's true operand (#105786)

2024-08-27 01:11:46 +08:00

rvv-peephole-vmerge-to-vmv.mir

[RISCV] Check vmerge's true is in same block in vmerge -> vmv.v.v peephole (#110861)

2024-10-03 12:02:54 +08:00

rvv-peephole-vmerge-vops-mir.ll

[RISCV] Add unit strided load/store to whole register peephole (#100116)

2024-07-24 11:52:54 +08:00

rvv-peephole-vmerge-vops.ll

[Test] Fix usage of constrained intrinsics (#113523)

2024-10-28 14:07:32 +07:00

rvv-stack-align.mir

…

rvv-vmerge-to-vmv.ll

…

rvv-vscale.i32.ll

…

rvv-vscale.i64.ll

…

saddo-sdnode.ll

…

scalable-vector-struct.ll

…

scalar-stack-align.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

select-bf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

select-fp.ll

[RISCV] Remove duplicate bf16 testing. NFC

2024-06-13 20:05:24 -07:00

select-int.ll

…

select-sra.ll

…

setcc-fp-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

setcc-fp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

setcc-int-vp-mask.ll

…

setcc-int-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

setcc-integer.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

sf_vfnrclip_x_f_qf.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

sf_vfnrclip_xu_f_qf.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

sf_vfwmacc_4x4x4.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

sf_vqmacc_2x8x2.ll

…

sf_vqmacc_4x8x4.ll

…

sf_vqmaccsu_2x8x2.ll

…

sf_vqmaccsu_4x8x4.ll

…

sf_vqmaccu_2x8x2.ll

…

sf_vqmaccu_4x8x4.ll

…

sf_vqmaccus_2x8x2.ll

…

sf_vqmaccus_4x8x4.ll

…

sink-splat-operands-i1.ll

…

sink-splat-operands.ll

[RISCV] Add reversed select testcase for canSplatOperand [nfc]

2024-09-24 15:52:03 -07:00

smulo-sdnode.ll

…

splat-vector-split-i64-vl-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

splat-vectors.ll

…

splats-with-mixed-vl.ll

…

sshl_sat_vec.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

stack-coloring-scalablevec.mir

…

stack-folding.ll

[RISCV] Update stack-folding.ll test

2024-10-01 14:35:10 +08:00

stepvector.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

store-bf16.ll

[RISCV] Expand bf16 vector truncstores and extloads (#108235)

2024-09-12 08:42:25 +08:00

strided-load-store.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

strided-vpload-vpstore-output.ll

…

strided-vpload.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

strided-vpstore.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

subregister-undef-early-clobber.mir

[InitUndef] Don't use largest super class (#107885)

2024-09-11 09:36:20 +02:00

tail-agnostic-impdef-copy.mir

[NewPM][CodeGen] Port finalize-isel to new pass manager (#94214)

2024-06-04 09:23:52 +08:00

trunc-sat-clip-sdnode.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468)

2024-08-16 08:42:36 -07:00

trunc-select-to-max-usat.ll

[RISCV] Don't support TRUNCATE_SSAT_U. (#104468)

2024-08-16 08:42:36 -07:00

umulo-sdnode.ll

…

unaligned-loads-stores.ll

…

undef-earlyclobber-chain.ll

Move stepvector intrinsic out of experimental namespace (#98043)

2024-08-28 12:48:20 +01:00

undef-earlyclobber-chain.mir

[CodeGen] Add generic INIT_UNDEF pseudo (#106744)

2024-09-05 09:34:39 +02:00

undef-vp-ops.ll

[VP][RISCV] Add vp.reduce.fmaximum/fminimum and its RISC-V codegen (#91782)

2024-05-10 16:01:47 -07:00

unmasked-ta.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

unmasked-tu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

urem-seteq-vec.ll

…

ushl_sat_vec.ll

…

vaadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vaaddu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vaaddu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vadc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vadd-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vadd-vp-mask.ll

…

vadd-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vaesdf.ll

…

vaesdm.ll

…

vaesef.ll

…

vaesem.ll

…

vaeskf1.ll

…

vaeskf2.ll

…

vaesz.ll

…

vand-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vand-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vand.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vandn-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vandn-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vandn.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

variant-cc.ll

…

vasub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vasubu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vbrev8.ll

…

vbrev.ll

…

vclmul.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vclmulh.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vclz.ll

…

vcompress.ll

[RISCV] Support vrgather and vcompress for zvfhmin and zvfbfmin (#101633)

2024-08-06 18:00:16 +08:00

vcopysign-vp.ll

[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)

2024-08-30 09:44:51 -07:00

vcpop.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vcpopv.ll

…

vctz.ll

…

vdiv-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vdiv-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vdiv.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vdivu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vdivu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vdivu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vec3-setcc-crash.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vector-compress.ll

[RISCV] Lower @llvm.experimental.vector.compress for zvfhmin/zvfbfmin (#113770)

2024-10-28 09:37:06 +00:00

vector-deinterleave-fixed.ll

[RISCV] Reorder shuffle operands if one side is an identity (#98534)

2024-07-11 13:52:41 -07:00

vector-deinterleave-load.ll

[RISCV][llvm] Handle ptr element type in lowerDeinterleaveIntrinsicToLoad and lowerInterleaveIntrinsicToStore (#107079)

2024-09-05 12:46:20 +08:00

vector-deinterleave.ll

[RISCV] Lower interleave + deinterleave for zvfhmin and zvfbfmin (#108404)

2024-09-13 00:09:17 +08:00

vector-interleave-fixed.ll

…

vector-interleave-store.ll

[RISCV][llvm] Handle ptr element type in lowerDeinterleaveIntrinsicToLoad and lowerInterleaveIntrinsicToStore (#107079)

2024-09-05 12:46:20 +08:00

vector-interleave.ll

[RISCV] Lower interleave + deinterleave for zvfhmin and zvfbfmin (#108404)

2024-09-13 00:09:17 +08:00

vector-reassociations.ll

[RISCV] Move RISCVInsertVSETVLI to after phi elimination (#91440)

2024-05-15 11:44:32 +08:00

vector-splice.ll

[RISCV] Lower vector_splice on zvfhmin/zvfbfmin (#112579)

2024-10-16 21:40:18 +01:00

vexts-sdnode.ll

…

vfabs-sdnode.ll

[RISCV] Merge bf16 tests into respective tests. NFC

2024-09-12 18:41:46 +08:00

vfabs-vp.ll

[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)

2024-08-30 09:44:51 -07:00

vfadd-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfadd-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfadd-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vfadd.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfclass-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfclass-vp.ll

…

vfclass.ll

…

vfcmp-constrained-sdnode.ll

…

vfcmps-constrained-sdnode.ll

…

vfcopysign-sdnode.ll

[RISCV] Merge bf16 tests into respective tests. NFC

2024-09-12 18:41:46 +08:00

vfcvt-f-x.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfcvt-f-xu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfcvt-rtz-x-f.ll

…

vfcvt-rtz-xu-f.ll

…

vfcvt-x-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfcvt-xu-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfdiv-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfdiv-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfdiv-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vfdiv.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfirst-byte-compare-index.ll

[RISCV][LoopIdiomVectorize] Support VP intrinsics in LoopIdiomVectorize (#94082)

2024-07-02 18:48:28 -07:00

vfirst.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vfma-vp-combine.ll

[RISCV] Reverse default assumption about performance of vlseN.v vd, (rs1), x0 (#98205)

2024-07-10 07:35:56 -07:00

vfma-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vfmacc-vp.ll

…

vfmacc.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfmadd-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmadd-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmadd.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfmax-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmax-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmax.ll

…

vfmerge.ll

[RISCV] Remove isel patterns for riscv.vfmerge with vector-vector operands. (#101277)

2024-07-30 20:35:32 -07:00

vfmin-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmin-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmin.ll

…

vfmsac-vp.ll

…

vfmsac.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfmsub-constrained-sdnode.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfmsub-sdnode.ll

…

vfmsub.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfmul-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmul-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfmul-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vfmul.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfmuladd-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vfmv.f.s.ll

[RISCV] Remove vfmv.s.f and vfmv.f.s lmul pseudo variants (#100970)

2024-07-29 22:01:17 +08:00

vfmv.s.f.ll

[RISCV] Remove vfmv.s.f and vfmv.f.s lmul pseudo variants (#100970)

2024-07-29 22:01:17 +08:00

vfmv.v.f.ll

[RISCV] Remove unnecessary bf16 -mattr from vfmv.v.f.ll. NFC

2024-06-13 21:41:35 -07:00

vfncvt-f-f.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfncvt-f-x.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfncvt-f-xu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfncvt-rod-f-f.ll

…

vfncvt-rtz-x-f.ll

…

vfncvt-rtz-xu-f.ll

…

vfncvt-x-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfncvt-xu-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfncvtbf16-f-f.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfneg-sdnode.ll

[RISCV] Merge bf16 tests into respective tests. NFC

2024-09-12 18:41:46 +08:00

vfneg-vp.ll

[LegalizeVectorOps][RISCV] Don't promote VP_FABS/FNEG/FCOPYSIGN. (#106659)

2024-08-30 09:44:51 -07:00

vfnmacc-vp.ll

…

vfnmacc.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfnmadd-constrained-sdnode.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfnmadd-sdnode.ll

…

vfnmadd.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfnmsac-vp.ll

…

vfnmsac.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfnmsub-constrained-sdnode.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfnmsub-sdnode.ll

…

vfnmsub.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfpext-constrained-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfpext-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfpext-vp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfptoi-constrained-sdnode.ll

…

vfptoi-sdnode.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vfptosi-vp-mask.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vfptosi-vp.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vfptoui-vp-mask.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vfptoui-vp.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vfptrunc-constrained-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfptrunc-sdnode.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfptrunc-vp.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfrdiv-vp.ll

…

vfrdiv.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfrec7.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfredmax.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfredmin.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfredosum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfredusum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfrsqrt7.ll

…

vfrsub-vp.ll

…

vfrsub.ll

…

vfsgnj.ll

…

vfsgnjn.ll

…

vfsgnjx.ll

…

vfslide1down.ll

…

vfslide1up.ll

…

vfsqrt-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfsqrt-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfsqrt-vp.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfsqrt.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfsub-constrained-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfsub-sdnode.ll

[RISCV] Promote bf16 ops to f32 with zvfbfmin (#108937)

2024-09-18 17:39:40 +08:00

vfsub-vp.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vfsub.ll

…

vfwadd-sdnode.ll

…

vfwadd-vp.ll

[RISCV] Restrict combineOp_VLToVWOp_VL w/ bf16 to vfwmadd_vl with zvfbfwma (#108798)

2024-09-17 13:35:25 +08:00

vfwadd.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwadd.w.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwcvt-f-f.ll

…

vfwcvt-f-x.ll

…

vfwcvt-f-xu.ll

…

vfwcvt-rtz-x-f.ll

…

vfwcvt-rtz-xu-f.ll

…

vfwcvt-x-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfwcvt-xu-f.ll

[RISCV] Match vector fp-int convert intrinsics with specific RTZ rounding mode to the rtz variants (#98120)

2024-07-10 10:51:20 +08:00

vfwcvtbf16-f-f.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfwmacc-sdnode.ll

…

vfwmacc-vp.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfwmacc.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwmaccbf16-sdnode.ll

[RISCV] Add scalable vector patterns for vfwmaccbf16.v{v,f} (#106771)

2024-08-31 13:20:19 +08:00

vfwmaccbf16.ll

[RISCV] Remove experimental for bf16 extensions (#97996)

2024-07-09 14:34:03 +08:00

vfwmsac-vp.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfwmsac.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwmul-sdnode.ll

…

vfwmul.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwnmacc-vp.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfwnmacc.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwnmsac-vp.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vfwnmsac.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwredosum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfwredusum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vfwsub-sdnode.ll

…

vfwsub.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vfwsub.w.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vghsh.ll

…

vgmul.ll

…

vid.ll

…

viota.ll

…

vitofp-constrained-sdnode.ll

…

vitofp-sdnode.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vl-opt-instrs.ll

[RISCV][VLOPT] Add support for integer widening multiply instructions (#112204)

2024-10-16 09:37:27 -04:00

vl-opt-no-prop.ll

[RISCV][VLOPT] Update test cases to use riscv-enable-vl-optimizer and better formatting

2024-10-14 08:44:16 -07:00

vl-opt-op-info.ll

[RISCV][VLOPT] Fix passthru check in getOperandInfo (#112244)

2024-10-14 20:54:17 +01:00

vl-opt.ll

[RISCV][VLOPT] Allow propagation even when VL isn't VLMAX (#112228)

2024-10-16 14:58:00 -04:00

vl-opt.mir

[RISCV][VLOPT] Fix operand check in isVectorOpUsedAsScalarOp (#112253)

2024-10-15 15:10:26 +01:00

vle_vid-vfcvt.ll

…

vle.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vleff-vlseg2ff-output.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vleff.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vlm.ll

…

vlmax-peephole.ll

[RISCV] Convert AVLs with vlenb to VLMAX where possible (#97800)

2024-07-11 14:22:00 +08:00

vloxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vloxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vloxseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vloxseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlse.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vlseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsegff-rv32-dead.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsegff-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsegff-rv64-dead.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsegff-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vlsseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vluxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vluxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vluxseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vluxseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vmacc-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmacc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmadc.carry.in.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmadc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmadd-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmadd-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmand.ll

…

vmandn.ll

…

vmarith-sdnode.ll

…

vmax-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmax-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmax.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmaxu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmaxu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmaxu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmclr.ll

…

vmerge.ll

[RISCV] Add IR tests for bf16 vmerge and vmv.v.v. NFC (#102775)

2024-08-10 22:39:46 -07:00

vmfeq.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmfge.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmfgt.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmfle.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmflt.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmfne.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vmin-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmin-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmin.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vminu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vminu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vminu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmnand.ll

…

vmnor.ll

…

vmor.ll

…

vmorn.ll

…

vmsbc.borrow.in.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsbc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsbf.ll

[RISCV] Use ForceTailAgnostic for masked vmsbf/vmsif/vmsof.m. (#94532)

2024-06-05 14:20:38 -07:00

vmseq.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmset.ll

…

vmsge.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsgeu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsgt.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsgtu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsif.ll

[RISCV] Use ForceTailAgnostic for masked vmsbf/vmsif/vmsof.m. (#94532)

2024-06-05 14:20:38 -07:00

vmsle.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsleu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmslt.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsltu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsne.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmsof.ll

[RISCV] Use ForceTailAgnostic for masked vmsbf/vmsif/vmsof.m. (#94532)

2024-06-05 14:20:38 -07:00

vmul-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmul-vp-mask.ll

…

vmul-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmul.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmulh-sdnode.ll

…

vmulh.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmulhsu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmulhu-sdnode.ll

…

vmulhu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmv-copy.mir

…

vmv.s.x.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmv.v.v-peephole.ll

[RISCV] Fold PseudoVMV_V_V with undef passthru, handling policy (#106943)

2024-09-05 12:04:33 +08:00

vmv.v.v-peephole.mir

[RISCV] Model dest EEW and fix peepholes not checking EEW (#105945)

2024-09-05 15:27:48 +08:00

vmv.v.v.ll

[RISCV] Add passthru to vmv.v.v intrinsic tests. NFC

2024-09-04 13:51:32 +08:00

vmv.v.x.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vmv.x.s.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vmxnor.ll

…

vmxor.ll

…

vnclip.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vnclipu.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vnmsac-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vnmsac.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vnmsub-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vnmsub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vnsra-sdnode.ll

…

vnsra-vp.ll

…

vnsra.ll

…

vnsrl-sdnode.ll

…

vnsrl-vp.ll

…

vnsrl.ll

…

vor-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vor-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vor.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vp-cttz-elts.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vp-inttoptr-ptrtoint.ll

…

vp-reverse-float-fixed-vectors.ll

…

vp-reverse-float.ll

…

vp-reverse-int-fixed-vectors.ll

…

vp-reverse-int.ll

[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (#104574)

2024-08-29 14:32:41 +08:00

vp-reverse-mask-fixed-vectors.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vp-reverse-mask.ll

[RISCV] Decompose LMUL > 1 reverses into LMUL * M1 vrgather.vv (#104574)

2024-08-29 14:32:41 +08:00

vp-select.ll

[SelectionDAG] Simplify vselect true, T, F -> T (#100992)

2024-08-06 10:49:20 +08:00

vp-splat.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vp-splice-fixed-vectors.ll

…

vp-splice-mask-fixed-vectors.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vp-splice-mask-vectors.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vp-splice.ll

…

vpgather-sdnode.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

vpload.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

vpmerge-sdnode-bf16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vpmerge-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vpscatter-sdnode.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vpstore.ll

[RISCV] Lower memory ops and VP splat for zvfhmin and zvfbfmin (#109387)

2024-09-26 01:47:46 +08:00

vredand.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredmax.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredmaxu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredmin.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredminu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredor.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vredsum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vreductions-fp-sdnode.ll

[DAG][RISCV] Use vp_reduce_fadd/fmul when widening types for FP reductions (#105840)

2024-08-24 10:47:57 -07:00

vreductions-fp-vp.ll

[SDAG][RISCV] Don't promote VP_REDUCE_{FADD,FMUL} (#111000)

2024-10-04 00:17:45 +08:00

vreductions-int-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vreductions-int.ll

…

vreductions-mask-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vreductions-mask.ll

…

vredxor.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vrem-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vrem-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vrem.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vremu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vremu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vremu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vrev8.ll

…

vrgather.ll

[RISCV] Support vrgather and vcompress for zvfhmin and zvfbfmin (#101633)

2024-08-06 18:00:16 +08:00

vrgatherei16-subreg-liveness.ll

[CodeGen] Remove target SubRegLiveness flags (#95437)

2024-06-14 08:51:56 +01:00

vrgatherei16.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vrol-sdnode.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

vrol.ll

…

vror-sdnode.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

vror.ll

…

vrsub-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vrsub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vrsub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsadd-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsadd-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsadd.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsaddu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsaddu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsaddu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsbc.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vscale-power-of-two.ll

…

vscale-vw-web-simplification.ll

…

vse.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vselect-bf16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vselect-fp.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vselect-int.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vselect-mask.ll

…

vselect-vp-bf16.ll

[RISCV] Remove Zfbfmin from some vector test RUN lines. NFC

2024-07-31 22:25:23 -07:00

vselect-vp.ll

[RISCV] Remove duplicate bf16 testing. NFC

2024-06-13 20:05:24 -07:00

vsetvl-ext.ll

…

vsetvli-insert-crossbb.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

vsetvli-insert-crossbb.mir

[RISCV] Copy AVLs whose LiveIntervals aren't extendable in insertVSETVLI (#98342)

2024-07-15 13:18:12 +08:00

vsetvli-insert-O0.ll

[RISCV] Teach RISCVInsertVSETVLI to work without LiveIntervals

2024-06-17 12:05:43 -07:00

vsetvli-insert.ll

[RISCV] Relax RISCVInsertVSETVLI output VL peeking to cover registers (#96200)

2024-06-23 20:20:59 +08:00

vsetvli-insert.mir

[RISCV] Prune dead LI in vsetvli coalescing with trivially dead vsetvli (#98647)

2024-07-15 08:36:20 -07:00

vsetvli-intrinsics.ll

…

vsetvli-regression.ll

[RISCV] Remove hasSideEffects=1 for vsetvli pseudos (#91319)

2024-05-15 23:37:31 +08:00

vsetvli-valid-elen-fp.ll

…

vsetvlmax-ext.ll

…

vsext-vp-mask.ll

…

vsext-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vsext.ll

…

vsha2ch.ll

…

vsha2cl.ll

…

vsha2ms.ll

…

vshl-sdnode.ll

…

vshl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

vsitofp-vp-mask.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vsitofp-vp.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vslide1down-constant-vl-rv32.ll

[RISCV] Use X0 for VLMax for slide1up/slide1down in lowerVectorIntrinsicScalars. (#101384)

2024-07-31 13:01:31 -07:00

vslide1down.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vslide1up-constant-vl-rv32.ll

[RISCV] Use X0 for VLMax for slide1up/slide1down in lowerVectorIntrinsicScalars. (#101384)

2024-07-31 13:01:31 -07:00

vslide1up.ll

[RISCV] Merge more rv32/rv64 intrtinsic tests that have (or should have) the same content. NFC

2024-07-30 16:20:37 -07:00

vslidedown.ll

…

vslideup.ll

…

vsll.ll

[RISCV] Make the vsll->vadd intrinsic pattern support tail undisturbed intrinsics.

2024-06-05 11:34:41 -07:00

vsm3c.ll

…

vsm3me.ll

…

vsm4k.ll

…

vsm4r.ll

…

vsm.ll

…

vsmul.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsoxei-rv64.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsoxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsoxseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vsoxseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vsplats-bf16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vsplats-f16.ll

[RISCV] Lower f16/bf16 splat_vector by bitcasting to i16 instead of promoting to f32. (#108298)

2024-09-11 22:29:20 -07:00

vsplats-fp.ll

[RISCV] Add splat tests for zvfbfmin and without zfhmin/zfbfmin. NFC

2024-09-25 19:41:17 +08:00

vsplats-i1.ll

…

vsplats-i64.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsplats-zfa.ll

…

vsra-sdnode.ll

[RISCV] Verify the VL and Mask on the outer TRUNCATE_VECTOR_VL in combineTruncOfSraSext. (#93578)

2024-05-29 11:53:01 -07:00

vsra-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

vsra.ll

…

vsrl-sdnode.ll

…

vsrl-vp.ll

[LegalizeTypes] Use VP_AND and VP_SHL/VP_SRA to promote operands fo VP arithmetic. (#92799)

2024-05-28 12:49:42 -07:00

vsrl.ll

…

vsse.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vsseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vssra-rv32.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vssra-rv64.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vssrl-rv32.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vssrl-rv64.ll

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vssseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vssseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vssub-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vssub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vssub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vssubu-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vssubu-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vssubu.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsub-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsub-vp-mask.ll

…

vsub-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsub.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vsuxei-rv64.ll

[RISCV] Add vector bf16 load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsuxei.ll

[RISCV] Replace Zvfh with Zvfhmin on vector load/store intrinsic tests. NFC

2024-07-31 23:30:44 -07:00

vsuxseg-rv32.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vsuxseg-rv64.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00

vtrunc-vp-mask.ll

…

vtrunc-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vtruncs-sdnode.ll

…

vuitofp-vp-mask.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vuitofp-vp.ll

[RISCV] Lower bf16 {S,U}INT_TO_FP, FP_TO_{S,U}INT and VP variants (#108338)

2024-09-13 13:04:56 +08:00

vwadd-mask-sdnode.ll

…

vwadd-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vwadd-vp.ll

…

vwadd.ll

…

vwadd.w.ll

…

vwaddu.ll

…

vwaddu.w.ll

…

vwmacc-sdnode.ll

…

vwmacc-vp.ll

…

vwmacc.ll

…

vwmaccsu-vp.ll

…

vwmaccsu.ll

…

vwmaccu-vp.ll

…

vwmaccu.ll

…

vwmaccus.ll

…

vwmul-sdnode.ll

…

vwmul.ll

…

vwmulsu.ll

…

vwmulu.ll

…

vwredsum.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vwredsumu.ll

[RISCV] Use TU policy for C reduction intrinsics. (#93970)

2024-05-31 14:03:02 -05:00

vwsll-sdnode.ll

[RISCV] Teach fillUpExtensionSupportForSplat to handle nxvXi64 VMV_V_X_VL on RV32. (#99251)

2024-07-17 12:23:05 -07:00

vwsll-vp.ll

…

vwsll.ll

…

vwsub-mask-sdnode.ll

…

vwsub-sdnode.ll

…

vwsub.ll

…

vwsub.w.ll

…

vwsubu.ll

…

vwsubu.w.ll

…

vxor-sdnode.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vxor-vp.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vxor.ll

[RISCV] Enable store clustering by default (#73796)

2024-10-11 20:25:53 +01:00

vxrm-insert.ll

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

vxrm.mir

[RISCV] Move RISCVInsertVSETVLI after CSR/VXRM passes (#91701)

2024-05-10 14:31:43 +08:00

vzext-vp-mask.ll

…

vzext-vp.ll

[RISCV] Support postRA vsetvl insertion pass (#70549)

2024-05-21 14:42:55 +08:00

vzext.ll

…

wrong-chain-fixed-load.ll

…

wrong-stack-offset-for-rvv-object.mir

[RISCV] Take known minimum vlen into account when calculating alignment padding in assignRVVStackObjectOffsets. (#110312)

2024-09-30 11:44:23 -07:00

wrong-stack-slot-rv32.mir

…

wrong-stack-slot-rv64.mir

…

xsfvcp-x.ll

…

xsfvcp-xv.ll

…

xsfvcp-xvv.ll

[RISCV][VCIX] Add a tied constraint between rd and rs3 in sf.v.xvv and sf.v.xvw instructions (#111630)

2024-10-14 21:10:55 -07:00

xsfvcp-xvw.ll

…

xtheadvdot-vmaqa.ll

…

xtheadvdot-vmaqasu.ll

…

xtheadvdot-vmaqau.ll

…

xtheadvdot-vmaqaus.ll

…

zve32-types.ll

[RISCV] Introduce local peephole to reduce VLs based on demanded VL (#104689)

2024-08-22 07:34:41 -07:00

zvlsseg-copy.mir

…

zvlsseg-spill.mir

…

zvlsseg-zero-vl.ll

[llvm][RISCV] Support RISCV vector tuple CodeGen and Calling Convention (#97995)

2024-08-31 19:28:36 +08:00