edac1b2d63
For f16 with zvfhmin, we promote most ops and VP ops to f32. This does the same for bf16 with zvfbfmin, so the two fp types should now be in sync. There are a few places in the custom lowering where we need to check for a LMUL 8 f16/bf16 vector that can't be promoted and must be split, this extracts that out into isPromotedOpNeedingSplit. In a follow up NFC we can deduplicate the code that sets up the promotions.
199 lines
7.5 KiB
LLVM
199 lines
7.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfh,+zvfh,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFH
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; RUN: llc -mtriple=riscv32 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=ilp32d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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; RUN: llc -mtriple=riscv64 -mattr=+d,+zfhmin,+zvfhmin,+zfbfmin,+zvfbfmin,+v \
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; RUN: -target-abi=lp64d -verify-machineinstrs < %s | FileCheck %s \
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; RUN: --check-prefixes=CHECK,ZVFHMIN
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define <vscale x 2 x i1> @isnan_nxv2bf16(<vscale x 2 x bfloat> %x) {
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; CHECK-LABEL: isnan_nxv2bf16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: lui a0, 8
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; CHECK-NEXT: addi a1, a0, -1
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; CHECK-NEXT: vsetvli a2, zero, e16, mf2, ta, ma
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; CHECK-NEXT: vand.vx v8, v8, a1
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; CHECK-NEXT: addi a0, a0, -128
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; CHECK-NEXT: vmsgt.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2bf16(<vscale x 2 x bfloat> %x, i32 3) ; nan
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ret <vscale x 2 x i1> %1
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}
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define <vscale x 2 x i1> @isnan_nxv2f16(<vscale x 2 x half> %x) {
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; ZVFH-LABEL: isnan_nxv2f16:
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; ZVFH: # %bb.0:
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; ZVFH-NEXT: vsetvli a0, zero, e16, mf2, ta, ma
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; ZVFH-NEXT: vfclass.v v8, v8
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; ZVFH-NEXT: li a0, 768
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; ZVFH-NEXT: vand.vx v8, v8, a0
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; ZVFH-NEXT: vmsne.vi v0, v8, 0
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; ZVFH-NEXT: ret
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;
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; ZVFHMIN-LABEL: isnan_nxv2f16:
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; ZVFHMIN: # %bb.0:
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; ZVFHMIN-NEXT: lui a0, 8
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; ZVFHMIN-NEXT: addi a0, a0, -1
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; ZVFHMIN-NEXT: vsetvli a1, zero, e16, mf2, ta, ma
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; ZVFHMIN-NEXT: vand.vx v8, v8, a0
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; ZVFHMIN-NEXT: li a0, 31
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; ZVFHMIN-NEXT: slli a0, a0, 10
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; ZVFHMIN-NEXT: vmsgt.vx v0, v8, a0
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; ZVFHMIN-NEXT: ret
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%1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half> %x, i32 3) ; nan
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ret <vscale x 2 x i1> %1
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}
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define <vscale x 2 x i1> @isnan_nxv2f32(<vscale x 2 x float> %x) {
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; CHECK-LABEL: isnan_nxv2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m1, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 927
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float> %x, i32 639)
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ret <vscale x 2 x i1> %1
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}
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define <vscale x 4 x i1> @isnan_nxv4f32(<vscale x 4 x float> %x) {
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; CHECK-LABEL: isnan_nxv4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 768
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float> %x, i32 3) ; nan
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ret <vscale x 4 x i1> %1
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}
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define <vscale x 8 x i1> @isnan_nxv8f32(<vscale x 8 x float> %x) {
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; CHECK-LABEL: isnan_nxv8f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m4, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 512
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float> %x, i32 2)
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ret <vscale x 8 x i1> %1
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}
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define <vscale x 16 x i1> @isnan_nxv16f32(<vscale x 16 x float> %x) {
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; CHECK-LABEL: isnan_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 256
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 1)
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ret <vscale x 16 x i1> %1
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}
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define <vscale x 2 x i1> @isnormal_nxv2f64(<vscale x 2 x double> %x) {
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; CHECK-LABEL: isnormal_nxv2f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m2, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 129
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double> %x, i32 516) ; 0x204 = "inf"
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ret <vscale x 2 x i1> %1
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}
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define <vscale x 4 x i1> @isposinf_nxv4f64(<vscale x 4 x double> %x) {
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; CHECK-LABEL: isposinf_nxv4f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m4, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 128
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; CHECK-NEXT: vmseq.vx v0, v8, a0
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; CHECK-NEXT: ret
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%1 = call <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double> %x, i32 512) ; 0x200 = "+inf"
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ret <vscale x 4 x i1> %1
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}
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define <vscale x 8 x i1> @isneginf_nxv8f64(<vscale x 8 x double> %x) {
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; CHECK-LABEL: isneginf_nxv8f64:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e64, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: vmseq.vi v0, v8, 1
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; CHECK-NEXT: ret
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%1 = call <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double> %x, i32 4) ; "-inf"
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ret <vscale x 8 x i1> %1
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}
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define <vscale x 16 x i1> @isfinite_nxv16f32(<vscale x 16 x float> %x) {
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; CHECK-LABEL: isfinite_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 126
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 504) ; 0x1f8 = "finite"
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ret <vscale x 16 x i1> %1
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}
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define <vscale x 16 x i1> @isposfinite_nxv16f32(<vscale x 16 x float> %x) {
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; CHECK-LABEL: isposfinite_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 112
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 448) ; 0x1c0 = "+finite"
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ret <vscale x 16 x i1> %1
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}
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define <vscale x 16 x i1> @isnegfinite_nxv16f32(<vscale x 16 x float> %x) {
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; CHECK-LABEL: isnegfinite_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: vand.vi v8, v8, 14
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 56) ; 0x38 = "-finite"
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ret <vscale x 16 x i1> %1
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}
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define <vscale x 16 x i1> @isnotfinite_nxv16f32(<vscale x 16 x float> %x) {
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; CHECK-LABEL: isnotfinite_nxv16f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetvli a0, zero, e32, m8, ta, ma
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; CHECK-NEXT: vfclass.v v8, v8
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; CHECK-NEXT: li a0, 897
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; CHECK-NEXT: vand.vx v8, v8, a0
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; CHECK-NEXT: vmsne.vi v0, v8, 0
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; CHECK-NEXT: ret
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%1 = call <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float> %x, i32 519) ; 0x207 = "inf|nan"
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ret <vscale x 16 x i1> %1
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}
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declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f16(<vscale x 2 x half>, i32)
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declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f32(<vscale x 2 x float>, i32)
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declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f32(<vscale x 4 x float>, i32)
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declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f32(<vscale x 8 x float>, i32)
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declare <vscale x 16 x i1> @llvm.is.fpclass.nxv16f32(<vscale x 16 x float>, i32)
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declare <vscale x 2 x i1> @llvm.is.fpclass.nxv2f64(<vscale x 2 x double>, i32)
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declare <vscale x 4 x i1> @llvm.is.fpclass.nxv4f64(<vscale x 4 x double>, i32)
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declare <vscale x 8 x i1> @llvm.is.fpclass.nxv8f64(<vscale x 8 x double>, i32)
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