b6dac89c87
Reviewers: aheejin, dschuff Subscribers: sbc100, jgravelle-google, sunfish, llvm-commits Differential Revision: https://reviews.llvm.org/D55956 llvm-svn: 349889
21 lines
694 B
LLVM
21 lines
694 B
LLVM
; RUN: llc < %s -mattr=+simd128,+sign-ext -verify-machineinstrs
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;; Ensures fastisel produces valid code when storing and loading split
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;; up v2i64 values. This is a regression test for a bug that crashed
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;; llc after fastisel produced machineinstrs that used registers that
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;; had never been defined.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown-wasm"
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define i64 @foo(<2 x i64> %vec) #0 {
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entry:
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%vec.addr = alloca <2 x i64>, align 16
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store <2 x i64> %vec, <2 x i64>* %vec.addr, align 16
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%0 = load <2 x i64>, <2 x i64>* %vec.addr, align 16
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%1 = extractelement <2 x i64> %0, i32 0
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ret i64 %1
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}
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attributes #0 = { noinline optnone }
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