396653f8a1
Relying on no spill or other code being inserted before this was precarious. It relied on code diligently checking isBasicBlockPrologue which is likely to be forgotten. Ideally this could be done earlier, but this doesn't work because of phis. Any other instruction can't be placed before them, so we have to accept the position being incorrect during SSA. This avoids regressions in the fast register allocator rewrite from inverting the direction. llvm-svn: 357634
369 lines
11 KiB
C++
369 lines
11 KiB
C++
//===-- SIOptimizeExecMasking.cpp -----------------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "AMDGPU.h"
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#include "AMDGPUSubtarget.h"
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#include "SIInstrInfo.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "llvm/ADT/SmallSet.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineRegisterInfo.h"
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#include "llvm/Support/Debug.h"
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using namespace llvm;
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#define DEBUG_TYPE "si-optimize-exec-masking"
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namespace {
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class SIOptimizeExecMasking : public MachineFunctionPass {
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public:
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static char ID;
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public:
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SIOptimizeExecMasking() : MachineFunctionPass(ID) {
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initializeSIOptimizeExecMaskingPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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StringRef getPassName() const override {
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return "SI optimize exec mask operations";
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}
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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};
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} // End anonymous namespace.
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INITIALIZE_PASS_BEGIN(SIOptimizeExecMasking, DEBUG_TYPE,
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"SI optimize exec mask operations", false, false)
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INITIALIZE_PASS_DEPENDENCY(LiveIntervals)
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INITIALIZE_PASS_END(SIOptimizeExecMasking, DEBUG_TYPE,
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"SI optimize exec mask operations", false, false)
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char SIOptimizeExecMasking::ID = 0;
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char &llvm::SIOptimizeExecMaskingID = SIOptimizeExecMasking::ID;
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/// If \p MI is a copy from exec, return the register copied to.
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static unsigned isCopyFromExec(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::COPY:
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case AMDGPU::S_MOV_B64:
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case AMDGPU::S_MOV_B64_term: {
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const MachineOperand &Src = MI.getOperand(1);
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if (Src.isReg() && Src.getReg() == AMDGPU::EXEC)
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return MI.getOperand(0).getReg();
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}
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}
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return AMDGPU::NoRegister;
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}
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/// If \p MI is a copy to exec, return the register copied from.
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static unsigned isCopyToExec(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::COPY:
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case AMDGPU::S_MOV_B64: {
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const MachineOperand &Dst = MI.getOperand(0);
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if (Dst.isReg() && Dst.getReg() == AMDGPU::EXEC && MI.getOperand(1).isReg())
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return MI.getOperand(1).getReg();
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break;
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}
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case AMDGPU::S_MOV_B64_term:
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llvm_unreachable("should have been replaced");
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}
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return AMDGPU::NoRegister;
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}
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/// If \p MI is a logical operation on an exec value,
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/// return the register copied to.
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static unsigned isLogicalOpOnExec(const MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::S_AND_B64:
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case AMDGPU::S_OR_B64:
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case AMDGPU::S_XOR_B64:
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case AMDGPU::S_ANDN2_B64:
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case AMDGPU::S_ORN2_B64:
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case AMDGPU::S_NAND_B64:
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case AMDGPU::S_NOR_B64:
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case AMDGPU::S_XNOR_B64: {
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const MachineOperand &Src1 = MI.getOperand(1);
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if (Src1.isReg() && Src1.getReg() == AMDGPU::EXEC)
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return MI.getOperand(0).getReg();
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const MachineOperand &Src2 = MI.getOperand(2);
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if (Src2.isReg() && Src2.getReg() == AMDGPU::EXEC)
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return MI.getOperand(0).getReg();
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}
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}
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return AMDGPU::NoRegister;
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}
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static unsigned getSaveExecOp(unsigned Opc) {
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switch (Opc) {
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case AMDGPU::S_AND_B64:
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return AMDGPU::S_AND_SAVEEXEC_B64;
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case AMDGPU::S_OR_B64:
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return AMDGPU::S_OR_SAVEEXEC_B64;
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case AMDGPU::S_XOR_B64:
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return AMDGPU::S_XOR_SAVEEXEC_B64;
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case AMDGPU::S_ANDN2_B64:
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return AMDGPU::S_ANDN2_SAVEEXEC_B64;
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case AMDGPU::S_ORN2_B64:
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return AMDGPU::S_ORN2_SAVEEXEC_B64;
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case AMDGPU::S_NAND_B64:
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return AMDGPU::S_NAND_SAVEEXEC_B64;
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case AMDGPU::S_NOR_B64:
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return AMDGPU::S_NOR_SAVEEXEC_B64;
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case AMDGPU::S_XNOR_B64:
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return AMDGPU::S_XNOR_SAVEEXEC_B64;
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default:
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return AMDGPU::INSTRUCTION_LIST_END;
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}
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}
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// These are only terminators to get correct spill code placement during
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// register allocation, so turn them back into normal instructions. Only one of
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// these is expected per block.
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static bool removeTerminatorBit(const SIInstrInfo &TII, MachineInstr &MI) {
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switch (MI.getOpcode()) {
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case AMDGPU::S_MOV_B64_term: {
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MI.setDesc(TII.get(AMDGPU::COPY));
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return true;
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}
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case AMDGPU::S_XOR_B64_term: {
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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MI.setDesc(TII.get(AMDGPU::S_XOR_B64));
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return true;
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}
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case AMDGPU::S_OR_B64_term: {
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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MI.setDesc(TII.get(AMDGPU::S_OR_B64));
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return true;
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}
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case AMDGPU::S_ANDN2_B64_term: {
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// This is only a terminator to get the correct spill code placement during
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// register allocation.
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MI.setDesc(TII.get(AMDGPU::S_ANDN2_B64));
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return true;
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}
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default:
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return false;
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}
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}
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static MachineBasicBlock::reverse_iterator fixTerminators(
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const SIInstrInfo &TII,
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MachineBasicBlock &MBB) {
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MachineBasicBlock::reverse_iterator I = MBB.rbegin(), E = MBB.rend();
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for (; I != E; ++I) {
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if (!I->isTerminator())
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return I;
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if (removeTerminatorBit(TII, *I))
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return I;
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}
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return E;
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}
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static MachineBasicBlock::reverse_iterator findExecCopy(
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const SIInstrInfo &TII,
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MachineBasicBlock &MBB,
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MachineBasicBlock::reverse_iterator I,
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unsigned CopyToExec) {
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const unsigned InstLimit = 25;
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auto E = MBB.rend();
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for (unsigned N = 0; N <= InstLimit && I != E; ++I, ++N) {
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unsigned CopyFromExec = isCopyFromExec(*I);
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if (CopyFromExec != AMDGPU::NoRegister)
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return I;
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}
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return E;
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}
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// XXX - Seems LivePhysRegs doesn't work correctly since it will incorrectly
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// repor tthe register as unavailable because a super-register with a lane mask
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// as unavailable.
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static bool isLiveOut(const MachineBasicBlock &MBB, unsigned Reg) {
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for (MachineBasicBlock *Succ : MBB.successors()) {
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if (Succ->isLiveIn(Reg))
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return true;
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}
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return false;
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}
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bool SIOptimizeExecMasking::runOnMachineFunction(MachineFunction &MF) {
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if (skipFunction(MF.getFunction()))
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return false;
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const GCNSubtarget &ST = MF.getSubtarget<GCNSubtarget>();
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const SIRegisterInfo *TRI = ST.getRegisterInfo();
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const SIInstrInfo *TII = ST.getInstrInfo();
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// Optimize sequences emitted for control flow lowering. They are originally
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// emitted as the separate operations because spill code may need to be
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// inserted for the saved copy of exec.
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//
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// x = copy exec
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// z = s_<op>_b64 x, y
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// exec = copy z
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// =>
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// x = s_<op>_saveexec_b64 y
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//
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for (MachineBasicBlock &MBB : MF) {
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MachineBasicBlock::reverse_iterator I = fixTerminators(*TII, MBB);
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MachineBasicBlock::reverse_iterator E = MBB.rend();
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if (I == E)
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continue;
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unsigned CopyToExec = isCopyToExec(*I);
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if (CopyToExec == AMDGPU::NoRegister)
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continue;
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// Scan backwards to find the def.
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auto CopyToExecInst = &*I;
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auto CopyFromExecInst = findExecCopy(*TII, MBB, I, CopyToExec);
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if (CopyFromExecInst == E) {
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auto PrepareExecInst = std::next(I);
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if (PrepareExecInst == E)
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continue;
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// Fold exec = COPY (S_AND_B64 reg, exec) -> exec = S_AND_B64 reg, exec
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if (CopyToExecInst->getOperand(1).isKill() &&
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isLogicalOpOnExec(*PrepareExecInst) == CopyToExec) {
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LLVM_DEBUG(dbgs() << "Fold exec copy: " << *PrepareExecInst);
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PrepareExecInst->getOperand(0).setReg(AMDGPU::EXEC);
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LLVM_DEBUG(dbgs() << "into: " << *PrepareExecInst << '\n');
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CopyToExecInst->eraseFromParent();
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}
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continue;
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}
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if (isLiveOut(MBB, CopyToExec)) {
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// The copied register is live out and has a second use in another block.
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LLVM_DEBUG(dbgs() << "Exec copy source register is live out\n");
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continue;
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}
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unsigned CopyFromExec = CopyFromExecInst->getOperand(0).getReg();
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MachineInstr *SaveExecInst = nullptr;
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SmallVector<MachineInstr *, 4> OtherUseInsts;
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for (MachineBasicBlock::iterator J
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= std::next(CopyFromExecInst->getIterator()), JE = I->getIterator();
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J != JE; ++J) {
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if (SaveExecInst && J->readsRegister(AMDGPU::EXEC, TRI)) {
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LLVM_DEBUG(dbgs() << "exec read prevents saveexec: " << *J << '\n');
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// Make sure this is inserted after any VALU ops that may have been
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// scheduled in between.
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SaveExecInst = nullptr;
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break;
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}
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bool ReadsCopyFromExec = J->readsRegister(CopyFromExec, TRI);
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if (J->modifiesRegister(CopyToExec, TRI)) {
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if (SaveExecInst) {
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LLVM_DEBUG(dbgs() << "Multiple instructions modify "
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<< printReg(CopyToExec, TRI) << '\n');
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SaveExecInst = nullptr;
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break;
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}
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unsigned SaveExecOp = getSaveExecOp(J->getOpcode());
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if (SaveExecOp == AMDGPU::INSTRUCTION_LIST_END)
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break;
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if (ReadsCopyFromExec) {
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SaveExecInst = &*J;
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LLVM_DEBUG(dbgs() << "Found save exec op: " << *SaveExecInst << '\n');
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continue;
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} else {
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LLVM_DEBUG(dbgs()
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<< "Instruction does not read exec copy: " << *J << '\n');
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break;
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}
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} else if (ReadsCopyFromExec && !SaveExecInst) {
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// Make sure no other instruction is trying to use this copy, before it
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// will be rewritten by the saveexec, i.e. hasOneUse. There may have
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// been another use, such as an inserted spill. For example:
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//
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// %sgpr0_sgpr1 = COPY %exec
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// spill %sgpr0_sgpr1
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// %sgpr2_sgpr3 = S_AND_B64 %sgpr0_sgpr1
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//
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LLVM_DEBUG(dbgs() << "Found second use of save inst candidate: " << *J
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<< '\n');
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break;
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}
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if (SaveExecInst && J->readsRegister(CopyToExec, TRI)) {
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assert(SaveExecInst != &*J);
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OtherUseInsts.push_back(&*J);
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}
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}
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if (!SaveExecInst)
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continue;
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LLVM_DEBUG(dbgs() << "Insert save exec op: " << *SaveExecInst << '\n');
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MachineOperand &Src0 = SaveExecInst->getOperand(1);
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MachineOperand &Src1 = SaveExecInst->getOperand(2);
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MachineOperand *OtherOp = nullptr;
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if (Src0.isReg() && Src0.getReg() == CopyFromExec) {
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OtherOp = &Src1;
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} else if (Src1.isReg() && Src1.getReg() == CopyFromExec) {
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if (!SaveExecInst->isCommutable())
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break;
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OtherOp = &Src0;
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} else
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llvm_unreachable("unexpected");
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CopyFromExecInst->eraseFromParent();
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auto InsPt = SaveExecInst->getIterator();
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const DebugLoc &DL = SaveExecInst->getDebugLoc();
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BuildMI(MBB, InsPt, DL, TII->get(getSaveExecOp(SaveExecInst->getOpcode())),
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CopyFromExec)
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.addReg(OtherOp->getReg());
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SaveExecInst->eraseFromParent();
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CopyToExecInst->eraseFromParent();
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for (MachineInstr *OtherInst : OtherUseInsts) {
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OtherInst->substituteRegister(CopyToExec, AMDGPU::EXEC,
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AMDGPU::NoSubRegister, *TRI);
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}
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}
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return true;
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}
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