2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
294 lines
12 KiB
C++
294 lines
12 KiB
C++
//===- ARMTargetStreamer.cpp - ARMTargetStreamer class --*- C++ -*---------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the ARMTargetStreamer class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/ARMMCTargetDesc.h"
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#include "llvm/MC/ConstantPools.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/ARMBuildAttributes.h"
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#include "llvm/Support/TargetParser.h"
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using namespace llvm;
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//
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// ARMTargetStreamer Implemenation
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//
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ARMTargetStreamer::ARMTargetStreamer(MCStreamer &S)
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: MCTargetStreamer(S), ConstantPools(new AssemblerConstantPools()) {}
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ARMTargetStreamer::~ARMTargetStreamer() = default;
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// The constant pool handling is shared by all ARMTargetStreamer
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// implementations.
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const MCExpr *ARMTargetStreamer::addConstantPoolEntry(const MCExpr *Expr, SMLoc Loc) {
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return ConstantPools->addEntry(Streamer, Expr, 4, Loc);
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}
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void ARMTargetStreamer::emitCurrentConstantPool() {
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ConstantPools->emitForCurrentSection(Streamer);
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ConstantPools->clearCacheForCurrentSection(Streamer);
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}
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// finish() - write out any non-empty assembler constant pools.
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void ARMTargetStreamer::finish() { ConstantPools->emitAll(Streamer); }
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// reset() - Reset any state
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void ARMTargetStreamer::reset() {}
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void ARMTargetStreamer::emitInst(uint32_t Inst, char Suffix) {
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unsigned Size;
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char Buffer[4];
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const bool LittleEndian = getStreamer().getContext().getAsmInfo()->isLittleEndian();
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switch (Suffix) {
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case '\0':
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Size = 4;
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for (unsigned II = 0, IE = Size; II != IE; II++) {
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const unsigned I = LittleEndian ? (Size - II - 1) : II;
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Buffer[Size - II - 1] = uint8_t(Inst >> I * CHAR_BIT);
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}
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break;
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case 'n':
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case 'w':
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Size = (Suffix == 'n' ? 2 : 4);
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// Thumb wide instructions are emitted as a pair of 16-bit words of the
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// appropriate endianness.
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for (unsigned II = 0, IE = Size; II != IE; II = II + 2) {
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const unsigned I0 = LittleEndian ? II + 0 : II + 1;
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const unsigned I1 = LittleEndian ? II + 1 : II + 0;
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Buffer[Size - II - 2] = uint8_t(Inst >> I0 * CHAR_BIT);
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Buffer[Size - II - 1] = uint8_t(Inst >> I1 * CHAR_BIT);
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}
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break;
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default:
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llvm_unreachable("Invalid Suffix");
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}
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getStreamer().EmitBytes(StringRef(Buffer, Size));
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}
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// The remaining callbacks should be handled separately by each
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// streamer.
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void ARMTargetStreamer::emitFnStart() {}
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void ARMTargetStreamer::emitFnEnd() {}
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void ARMTargetStreamer::emitCantUnwind() {}
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void ARMTargetStreamer::emitPersonality(const MCSymbol *Personality) {}
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void ARMTargetStreamer::emitPersonalityIndex(unsigned Index) {}
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void ARMTargetStreamer::emitHandlerData() {}
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void ARMTargetStreamer::emitSetFP(unsigned FpReg, unsigned SpReg,
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int64_t Offset) {}
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void ARMTargetStreamer::emitMovSP(unsigned Reg, int64_t Offset) {}
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void ARMTargetStreamer::emitPad(int64_t Offset) {}
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void ARMTargetStreamer::emitRegSave(const SmallVectorImpl<unsigned> &RegList,
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bool isVector) {}
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void ARMTargetStreamer::emitUnwindRaw(int64_t StackOffset,
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const SmallVectorImpl<uint8_t> &Opcodes) {
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}
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void ARMTargetStreamer::switchVendor(StringRef Vendor) {}
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void ARMTargetStreamer::emitAttribute(unsigned Attribute, unsigned Value) {}
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void ARMTargetStreamer::emitTextAttribute(unsigned Attribute,
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StringRef String) {}
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void ARMTargetStreamer::emitIntTextAttribute(unsigned Attribute,
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unsigned IntValue,
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StringRef StringValue) {}
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void ARMTargetStreamer::emitArch(ARM::ArchKind Arch) {}
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void ARMTargetStreamer::emitArchExtension(unsigned ArchExt) {}
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void ARMTargetStreamer::emitObjectArch(ARM::ArchKind Arch) {}
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void ARMTargetStreamer::emitFPU(unsigned FPU) {}
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void ARMTargetStreamer::finishAttributeSection() {}
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void
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ARMTargetStreamer::AnnotateTLSDescriptorSequence(const MCSymbolRefExpr *SRE) {}
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void ARMTargetStreamer::emitThumbSet(MCSymbol *Symbol, const MCExpr *Value) {}
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static ARMBuildAttrs::CPUArch getArchForCPU(const MCSubtargetInfo &STI) {
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if (STI.getCPU() == "xscale")
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return ARMBuildAttrs::v5TEJ;
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if (STI.hasFeature(ARM::HasV8Ops)) {
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if (STI.hasFeature(ARM::FeatureRClass))
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return ARMBuildAttrs::v8_R;
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return ARMBuildAttrs::v8_A;
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} else if (STI.hasFeature(ARM::HasV8MMainlineOps))
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return ARMBuildAttrs::v8_M_Main;
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else if (STI.hasFeature(ARM::HasV7Ops)) {
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if (STI.hasFeature(ARM::FeatureMClass) && STI.hasFeature(ARM::FeatureDSP))
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return ARMBuildAttrs::v7E_M;
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return ARMBuildAttrs::v7;
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} else if (STI.hasFeature(ARM::HasV6T2Ops))
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return ARMBuildAttrs::v6T2;
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else if (STI.hasFeature(ARM::HasV8MBaselineOps))
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return ARMBuildAttrs::v8_M_Base;
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else if (STI.hasFeature(ARM::HasV6MOps))
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return ARMBuildAttrs::v6S_M;
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else if (STI.hasFeature(ARM::HasV6Ops))
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return ARMBuildAttrs::v6;
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else if (STI.hasFeature(ARM::HasV5TEOps))
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return ARMBuildAttrs::v5TE;
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else if (STI.hasFeature(ARM::HasV5TOps))
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return ARMBuildAttrs::v5T;
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else if (STI.hasFeature(ARM::HasV4TOps))
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return ARMBuildAttrs::v4T;
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else
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return ARMBuildAttrs::v4;
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}
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static bool isV8M(const MCSubtargetInfo &STI) {
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// Note that v8M Baseline is a subset of v6T2!
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return (STI.hasFeature(ARM::HasV8MBaselineOps) &&
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!STI.hasFeature(ARM::HasV6T2Ops)) ||
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STI.hasFeature(ARM::HasV8MMainlineOps);
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}
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/// Emit the build attributes that only depend on the hardware that we expect
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// /to be available, and not on the ABI, or any source-language choices.
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void ARMTargetStreamer::emitTargetAttributes(const MCSubtargetInfo &STI) {
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switchVendor("aeabi");
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const StringRef CPUString = STI.getCPU();
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if (!CPUString.empty() && !CPUString.startswith("generic")) {
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// FIXME: remove krait check when GNU tools support krait cpu
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if (STI.hasFeature(ARM::ProcKrait)) {
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emitTextAttribute(ARMBuildAttrs::CPU_name, "cortex-a9");
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// We consider krait as a "cortex-a9" + hwdiv CPU
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// Enable hwdiv through ".arch_extension idiv"
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if (STI.hasFeature(ARM::FeatureHWDivThumb) ||
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STI.hasFeature(ARM::FeatureHWDivARM))
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emitArchExtension(ARM::AEK_HWDIVTHUMB | ARM::AEK_HWDIVARM);
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} else {
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emitTextAttribute(ARMBuildAttrs::CPU_name, CPUString);
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}
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}
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emitAttribute(ARMBuildAttrs::CPU_arch, getArchForCPU(STI));
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if (STI.hasFeature(ARM::FeatureAClass)) {
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emitAttribute(ARMBuildAttrs::CPU_arch_profile,
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ARMBuildAttrs::ApplicationProfile);
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} else if (STI.hasFeature(ARM::FeatureRClass)) {
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emitAttribute(ARMBuildAttrs::CPU_arch_profile,
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ARMBuildAttrs::RealTimeProfile);
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} else if (STI.hasFeature(ARM::FeatureMClass)) {
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emitAttribute(ARMBuildAttrs::CPU_arch_profile,
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ARMBuildAttrs::MicroControllerProfile);
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}
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emitAttribute(ARMBuildAttrs::ARM_ISA_use, STI.hasFeature(ARM::FeatureNoARM)
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? ARMBuildAttrs::Not_Allowed
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: ARMBuildAttrs::Allowed);
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if (isV8M(STI)) {
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emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
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ARMBuildAttrs::AllowThumbDerived);
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} else if (STI.hasFeature(ARM::FeatureThumb2)) {
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emitAttribute(ARMBuildAttrs::THUMB_ISA_use,
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ARMBuildAttrs::AllowThumb32);
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} else if (STI.hasFeature(ARM::HasV4TOps)) {
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emitAttribute(ARMBuildAttrs::THUMB_ISA_use, ARMBuildAttrs::Allowed);
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}
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if (STI.hasFeature(ARM::FeatureNEON)) {
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/* NEON is not exactly a VFP architecture, but GAS emit one of
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* neon/neon-fp-armv8/neon-vfpv4/vfpv3/vfpv2 for .fpu parameters */
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if (STI.hasFeature(ARM::FeatureFPARMv8)) {
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if (STI.hasFeature(ARM::FeatureCrypto))
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emitFPU(ARM::FK_CRYPTO_NEON_FP_ARMV8);
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else
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emitFPU(ARM::FK_NEON_FP_ARMV8);
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} else if (STI.hasFeature(ARM::FeatureVFP4))
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emitFPU(ARM::FK_NEON_VFPV4);
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else
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emitFPU(STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_NEON_FP16
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: ARM::FK_NEON);
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// Emit Tag_Advanced_SIMD_arch for ARMv8 architecture
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if (STI.hasFeature(ARM::HasV8Ops))
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emitAttribute(ARMBuildAttrs::Advanced_SIMD_arch,
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STI.hasFeature(ARM::HasV8_1aOps)
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? ARMBuildAttrs::AllowNeonARMv8_1a
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: ARMBuildAttrs::AllowNeonARMv8);
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} else {
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if (STI.hasFeature(ARM::FeatureFPARMv8))
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// FPv5 and FP-ARMv8 have the same instructions, so are modeled as one
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// FPU, but there are two different names for it depending on the CPU.
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emitFPU(STI.hasFeature(ARM::FeatureD16)
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? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV5_SP_D16
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: ARM::FK_FPV5_D16)
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: ARM::FK_FP_ARMV8);
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else if (STI.hasFeature(ARM::FeatureVFP4))
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emitFPU(STI.hasFeature(ARM::FeatureD16)
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? (STI.hasFeature(ARM::FeatureVFPOnlySP) ? ARM::FK_FPV4_SP_D16
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: ARM::FK_VFPV4_D16)
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: ARM::FK_VFPV4);
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else if (STI.hasFeature(ARM::FeatureVFP3))
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emitFPU(
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STI.hasFeature(ARM::FeatureD16)
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// +d16
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? (STI.hasFeature(ARM::FeatureVFPOnlySP)
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? (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3XD_FP16
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: ARM::FK_VFPV3XD)
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: (STI.hasFeature(ARM::FeatureFP16)
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? ARM::FK_VFPV3_D16_FP16
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: ARM::FK_VFPV3_D16))
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// -d16
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: (STI.hasFeature(ARM::FeatureFP16) ? ARM::FK_VFPV3_FP16
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: ARM::FK_VFPV3));
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else if (STI.hasFeature(ARM::FeatureVFP2))
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emitFPU(ARM::FK_VFPV2);
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}
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// ABI_HardFP_use attribute to indicate single precision FP.
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if (STI.hasFeature(ARM::FeatureVFPOnlySP))
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emitAttribute(ARMBuildAttrs::ABI_HardFP_use,
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ARMBuildAttrs::HardFPSinglePrecision);
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if (STI.hasFeature(ARM::FeatureFP16))
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emitAttribute(ARMBuildAttrs::FP_HP_extension, ARMBuildAttrs::AllowHPFP);
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if (STI.hasFeature(ARM::FeatureMP))
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emitAttribute(ARMBuildAttrs::MPextension_use, ARMBuildAttrs::AllowMP);
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// Hardware divide in ARM mode is part of base arch, starting from ARMv8.
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// If only Thumb hwdiv is present, it must also be in base arch (ARMv7-R/M).
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// It is not possible to produce DisallowDIV: if hwdiv is present in the base
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// arch, supplying -hwdiv downgrades the effective arch, via ClearImpliedBits.
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// AllowDIVExt is only emitted if hwdiv isn't available in the base arch;
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// otherwise, the default value (AllowDIVIfExists) applies.
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if (STI.hasFeature(ARM::FeatureHWDivARM) && !STI.hasFeature(ARM::HasV8Ops))
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emitAttribute(ARMBuildAttrs::DIV_use, ARMBuildAttrs::AllowDIVExt);
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if (STI.hasFeature(ARM::FeatureDSP) && isV8M(STI))
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emitAttribute(ARMBuildAttrs::DSP_extension, ARMBuildAttrs::Allowed);
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if (STI.hasFeature(ARM::FeatureStrictAlign))
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emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
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ARMBuildAttrs::Not_Allowed);
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else
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emitAttribute(ARMBuildAttrs::CPU_unaligned_access,
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ARMBuildAttrs::Allowed);
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if (STI.hasFeature(ARM::FeatureTrustZone) &&
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STI.hasFeature(ARM::FeatureVirtualization))
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emitAttribute(ARMBuildAttrs::Virtualization_use,
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ARMBuildAttrs::AllowTZVirtualization);
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else if (STI.hasFeature(ARM::FeatureTrustZone))
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emitAttribute(ARMBuildAttrs::Virtualization_use, ARMBuildAttrs::AllowTZ);
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else if (STI.hasFeature(ARM::FeatureVirtualization))
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emitAttribute(ARMBuildAttrs::Virtualization_use,
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ARMBuildAttrs::AllowVirtualization);
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}
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