Summary: Add __kernel_rt_sigreturn to the list of trap handlers for Linux (it's used as such on aarch64 at least), and __restore_rt as well (used on x86_64). Skip decrement-and-recompute for trap handlers in InitializeNonZerothFrame, as signal dispatch may point the child frame's return address to the start of the return trampoline. Parse the 'S' flag for signal handlers from eh_frame augmentation, and propagate it to the unwind plan. Reviewers: labath, jankratochvil, compnerd, jfb, jasonmolenda Reviewed By: jasonmolenda Subscribers: clayborg, MaskRay, wuzish, nemanjai, kbarton, jrtc27, atanasyan, jsji, javed.absar, kristof.beyls, lldb-commits Tags: #lldb Differential Revision: https://reviews.llvm.org/D63667 llvm-svn: 366580
399 lines
12 KiB
C++
399 lines
12 KiB
C++
//===-- EmulateInstructionPPC64.cpp ------------------------------*- C++-*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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#include "EmulateInstructionPPC64.h"
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#include <stdlib.h>
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#include "lldb/Core/PluginManager.h"
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#include "lldb/Symbol/UnwindPlan.h"
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#include "lldb/Utility/ArchSpec.h"
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#include "lldb/Utility/ConstString.h"
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#include "Plugins/Process/Utility/lldb-ppc64le-register-enums.h"
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#define DECLARE_REGISTER_INFOS_PPC64LE_STRUCT
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#include "Plugins/Process/Utility/RegisterInfos_ppc64le.h"
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#include "Plugins/Process/Utility/InstructionUtils.h"
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using namespace lldb;
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using namespace lldb_private;
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EmulateInstructionPPC64::EmulateInstructionPPC64(const ArchSpec &arch)
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: EmulateInstruction(arch) {}
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void EmulateInstructionPPC64::Initialize() {
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PluginManager::RegisterPlugin(GetPluginNameStatic(),
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GetPluginDescriptionStatic(), CreateInstance);
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}
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void EmulateInstructionPPC64::Terminate() {
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PluginManager::UnregisterPlugin(CreateInstance);
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}
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ConstString EmulateInstructionPPC64::GetPluginNameStatic() {
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ConstString g_plugin_name("lldb.emulate-instruction.ppc64");
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return g_plugin_name;
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}
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ConstString EmulateInstructionPPC64::GetPluginName() {
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static ConstString g_plugin_name("EmulateInstructionPPC64");
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return g_plugin_name;
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}
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const char *EmulateInstructionPPC64::GetPluginDescriptionStatic() {
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return "Emulate instructions for the PPC64 architecture.";
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}
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EmulateInstruction *
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EmulateInstructionPPC64::CreateInstance(const ArchSpec &arch,
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InstructionType inst_type) {
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if (EmulateInstructionPPC64::SupportsEmulatingInstructionsOfTypeStatic(
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inst_type))
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if (arch.GetTriple().isPPC64())
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return new EmulateInstructionPPC64(arch);
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return nullptr;
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}
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bool EmulateInstructionPPC64::SetTargetTriple(const ArchSpec &arch) {
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return arch.GetTriple().isPPC64();
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}
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static bool LLDBTableGetRegisterInfo(uint32_t reg_num, RegisterInfo ®_info) {
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if (reg_num >= llvm::array_lengthof(g_register_infos_ppc64le))
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return false;
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reg_info = g_register_infos_ppc64le[reg_num];
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return true;
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}
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bool EmulateInstructionPPC64::GetRegisterInfo(RegisterKind reg_kind,
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uint32_t reg_num,
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RegisterInfo ®_info) {
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if (reg_kind == eRegisterKindGeneric) {
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switch (reg_num) {
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case LLDB_REGNUM_GENERIC_PC:
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reg_kind = eRegisterKindLLDB;
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reg_num = gpr_pc_ppc64le;
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break;
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case LLDB_REGNUM_GENERIC_SP:
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reg_kind = eRegisterKindLLDB;
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reg_num = gpr_r1_ppc64le;
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break;
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case LLDB_REGNUM_GENERIC_RA:
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reg_kind = eRegisterKindLLDB;
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reg_num = gpr_lr_ppc64le;
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break;
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case LLDB_REGNUM_GENERIC_FLAGS:
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reg_kind = eRegisterKindLLDB;
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reg_num = gpr_cr_ppc64le;
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break;
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default:
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return false;
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}
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}
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if (reg_kind == eRegisterKindLLDB)
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return LLDBTableGetRegisterInfo(reg_num, reg_info);
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return false;
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}
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bool EmulateInstructionPPC64::ReadInstruction() {
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bool success = false;
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m_addr = ReadRegisterUnsigned(eRegisterKindGeneric, LLDB_REGNUM_GENERIC_PC,
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LLDB_INVALID_ADDRESS, &success);
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if (success) {
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Context ctx;
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ctx.type = eContextReadOpcode;
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ctx.SetNoArgs();
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m_opcode.SetOpcode32(ReadMemoryUnsigned(ctx, m_addr, 4, 0, &success),
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GetByteOrder());
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}
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if (!success)
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m_addr = LLDB_INVALID_ADDRESS;
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return success;
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}
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bool EmulateInstructionPPC64::CreateFunctionEntryUnwind(
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UnwindPlan &unwind_plan) {
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unwind_plan.Clear();
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unwind_plan.SetRegisterKind(eRegisterKindLLDB);
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UnwindPlan::RowSP row(new UnwindPlan::Row);
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// Our previous Call Frame Address is the stack pointer
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row->GetCFAValue().SetIsRegisterPlusOffset(gpr_r1_ppc64le, 0);
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unwind_plan.AppendRow(row);
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unwind_plan.SetSourceName("EmulateInstructionPPC64");
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unwind_plan.SetSourcedFromCompiler(eLazyBoolNo);
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unwind_plan.SetUnwindPlanValidAtAllInstructions(eLazyBoolYes);
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unwind_plan.SetUnwindPlanForSignalTrap(eLazyBoolNo);
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unwind_plan.SetReturnAddressRegister(gpr_lr_ppc64le);
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return true;
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}
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EmulateInstructionPPC64::Opcode *
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EmulateInstructionPPC64::GetOpcodeForInstruction(uint32_t opcode) {
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static EmulateInstructionPPC64::Opcode g_opcodes[] = {
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{0xfc0007ff, 0x7c0002a6, &EmulateInstructionPPC64::EmulateMFSPR,
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"mfspr RT, SPR"},
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{0xfc000003, 0xf8000000, &EmulateInstructionPPC64::EmulateSTD,
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"std RS, DS(RA)"},
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{0xfc000003, 0xf8000001, &EmulateInstructionPPC64::EmulateSTD,
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"stdu RS, DS(RA)"},
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{0xfc0007fe, 0x7c000378, &EmulateInstructionPPC64::EmulateOR,
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"or RA, RS, RB"},
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{0xfc000000, 0x38000000, &EmulateInstructionPPC64::EmulateADDI,
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"addi RT, RA, SI"},
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{0xfc000003, 0xe8000000, &EmulateInstructionPPC64::EmulateLD,
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"ld RT, DS(RA)"}};
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static const size_t k_num_ppc_opcodes = llvm::array_lengthof(g_opcodes);
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for (size_t i = 0; i < k_num_ppc_opcodes; ++i) {
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if ((g_opcodes[i].mask & opcode) == g_opcodes[i].value)
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return &g_opcodes[i];
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}
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return nullptr;
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}
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bool EmulateInstructionPPC64::EvaluateInstruction(uint32_t evaluate_options) {
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const uint32_t opcode = m_opcode.GetOpcode32();
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// LLDB_LOG(log, "PPC64::EvaluateInstruction: opcode={0:X+8}", opcode);
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Opcode *opcode_data = GetOpcodeForInstruction(opcode);
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if (!opcode_data)
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return false;
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// LLDB_LOG(log, "PPC64::EvaluateInstruction: {0}", opcode_data->name);
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const bool auto_advance_pc =
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evaluate_options & eEmulateInstructionOptionAutoAdvancePC;
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bool success = false;
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uint32_t orig_pc_value = 0;
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if (auto_advance_pc) {
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orig_pc_value =
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ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_ppc64le, 0, &success);
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if (!success)
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return false;
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}
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// Call the Emulate... function.
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success = (this->*opcode_data->callback)(opcode);
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if (!success)
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return false;
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if (auto_advance_pc) {
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uint32_t new_pc_value =
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ReadRegisterUnsigned(eRegisterKindLLDB, gpr_pc_ppc64le, 0, &success);
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if (!success)
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return false;
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if (auto_advance_pc && (new_pc_value == orig_pc_value)) {
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EmulateInstruction::Context context;
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context.type = eContextAdvancePC;
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context.SetNoArgs();
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if (!WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_pc_ppc64le,
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orig_pc_value + 4))
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return false;
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}
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}
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return true;
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}
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bool EmulateInstructionPPC64::EmulateMFSPR(uint32_t opcode) {
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uint32_t rt = Bits32(opcode, 25, 21);
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uint32_t spr = Bits32(opcode, 20, 11);
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enum { SPR_LR = 0x100 };
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// For now, we're only insterested in 'mfspr r0, lr'
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if (rt != gpr_r0_ppc64le || spr != SPR_LR)
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return false;
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Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
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LLDB_LOG(log, "EmulateMFSPR: {0:X+8}: mfspr r0, lr", m_addr);
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bool success;
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uint64_t lr =
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ReadRegisterUnsigned(eRegisterKindLLDB, gpr_lr_ppc64le, 0, &success);
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if (!success)
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return false;
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Context context;
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context.type = eContextWriteRegisterRandomBits;
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WriteRegisterUnsigned(context, eRegisterKindLLDB, gpr_r0_ppc64le, lr);
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LLDB_LOG(log, "EmulateMFSPR: success!");
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return true;
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}
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bool EmulateInstructionPPC64::EmulateLD(uint32_t opcode) {
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uint32_t rt = Bits32(opcode, 25, 21);
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uint32_t ra = Bits32(opcode, 20, 16);
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uint32_t ds = Bits32(opcode, 15, 2);
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int32_t ids = llvm::SignExtend32<16>(ds << 2);
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// For now, tracking only loads from 0(r1) to r1 (0(r1) is the ABI defined
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// location to save previous SP)
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if (ra != gpr_r1_ppc64le || rt != gpr_r1_ppc64le || ids != 0)
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return false;
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Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
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LLDB_LOG(log, "EmulateLD: {0:X+8}: ld r{1}, {2}(r{3})", m_addr, rt, ids, ra);
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RegisterInfo r1_info;
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if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
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return false;
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// restore SP
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Context ctx;
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ctx.type = eContextRestoreStackPointer;
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ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
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WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_ppc64le, 0);
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LLDB_LOG(log, "EmulateLD: success!");
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return true;
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}
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bool EmulateInstructionPPC64::EmulateSTD(uint32_t opcode) {
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uint32_t rs = Bits32(opcode, 25, 21);
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uint32_t ra = Bits32(opcode, 20, 16);
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uint32_t ds = Bits32(opcode, 15, 2);
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uint32_t u = Bits32(opcode, 1, 0);
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// For now, tracking only stores to r1
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if (ra != gpr_r1_ppc64le)
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return false;
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// ... and only stores of SP, FP and LR (moved into r0 by a previous mfspr)
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if (rs != gpr_r1_ppc64le && rs != gpr_r31_ppc64le && rs != gpr_r30_ppc64le &&
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rs != gpr_r0_ppc64le)
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return false;
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bool success;
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uint64_t rs_val = ReadRegisterUnsigned(eRegisterKindLLDB, rs, 0, &success);
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if (!success)
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return false;
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int32_t ids = llvm::SignExtend32<16>(ds << 2);
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Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
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LLDB_LOG(log, "EmulateSTD: {0:X+8}: std{1} r{2}, {3}(r{4})", m_addr,
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u ? "u" : "", rs, ids, ra);
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// Make sure that r0 is really holding LR value (this won't catch unlikely
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// cases, such as r0 being overwritten after mfspr)
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uint32_t rs_num = rs;
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if (rs == gpr_r0_ppc64le) {
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uint64_t lr =
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ReadRegisterUnsigned(eRegisterKindLLDB, gpr_lr_ppc64le, 0, &success);
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if (!success || lr != rs_val)
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return false;
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rs_num = gpr_lr_ppc64le;
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}
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// set context
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RegisterInfo rs_info;
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if (!GetRegisterInfo(eRegisterKindLLDB, rs_num, rs_info))
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return false;
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RegisterInfo ra_info;
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if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
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return false;
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Context ctx;
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ctx.type = eContextPushRegisterOnStack;
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ctx.SetRegisterToRegisterPlusOffset(rs_info, ra_info, ids);
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// store
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uint64_t ra_val = ReadRegisterUnsigned(eRegisterKindLLDB, ra, 0, &success);
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if (!success)
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return false;
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lldb::addr_t addr = ra_val + ids;
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WriteMemory(ctx, addr, &rs_val, sizeof(rs_val));
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// update RA?
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if (u) {
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Context ctx;
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// NOTE Currently, RA will always be equal to SP(r1)
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ctx.type = eContextAdjustStackPointer;
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WriteRegisterUnsigned(ctx, eRegisterKindLLDB, ra, addr);
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}
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LLDB_LOG(log, "EmulateSTD: success!");
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return true;
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}
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bool EmulateInstructionPPC64::EmulateOR(uint32_t opcode) {
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uint32_t rs = Bits32(opcode, 25, 21);
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uint32_t ra = Bits32(opcode, 20, 16);
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uint32_t rb = Bits32(opcode, 15, 11);
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// to be safe, process only the known 'mr r31/r30, r1' prologue instructions
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if (m_fp != LLDB_INVALID_REGNUM || rs != rb ||
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(ra != gpr_r30_ppc64le && ra != gpr_r31_ppc64le) || rb != gpr_r1_ppc64le)
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return false;
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Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
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LLDB_LOG(log, "EmulateOR: {0:X+8}: mr r{1}, r{2}", m_addr, ra, rb);
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// set context
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RegisterInfo ra_info;
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if (!GetRegisterInfo(eRegisterKindLLDB, ra, ra_info))
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return false;
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Context ctx;
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ctx.type = eContextSetFramePointer;
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ctx.SetRegister(ra_info);
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// move
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bool success;
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uint64_t rb_val = ReadRegisterUnsigned(eRegisterKindLLDB, rb, 0, &success);
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if (!success)
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return false;
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WriteRegisterUnsigned(ctx, eRegisterKindLLDB, ra, rb_val);
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m_fp = ra;
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LLDB_LOG(log, "EmulateOR: success!");
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return true;
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}
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bool EmulateInstructionPPC64::EmulateADDI(uint32_t opcode) {
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uint32_t rt = Bits32(opcode, 25, 21);
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uint32_t ra = Bits32(opcode, 20, 16);
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uint32_t si = Bits32(opcode, 15, 0);
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// handle stack adjustments only
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// (this is a typical epilogue operation, with ra == r1. If it's
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// something else, then we won't know the correct value of ra)
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if (rt != gpr_r1_ppc64le || ra != gpr_r1_ppc64le)
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return false;
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int32_t si_val = llvm::SignExtend32<16>(si);
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Log *log(GetLogIfAllCategoriesSet(LIBLLDB_LOG_UNWIND));
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LLDB_LOG(log, "EmulateADDI: {0:X+8}: addi r1, r1, {1}", m_addr, si_val);
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// set context
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RegisterInfo r1_info;
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if (!GetRegisterInfo(eRegisterKindLLDB, gpr_r1_ppc64le, r1_info))
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return false;
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Context ctx;
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ctx.type = eContextRestoreStackPointer;
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ctx.SetRegisterToRegisterPlusOffset(r1_info, r1_info, 0);
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// adjust SP
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bool success;
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uint64_t r1 =
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ReadRegisterUnsigned(eRegisterKindLLDB, gpr_r1_ppc64le, 0, &success);
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if (!success)
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return false;
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WriteRegisterUnsigned(ctx, eRegisterKindLLDB, gpr_r1_ppc64le, r1 + si_val);
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LLDB_LOG(log, "EmulateADDI: success!");
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return true;
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}
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