2946cd7010
to reflect the new license. We understand that people may be surprised that we're moving the header entirely to discuss the new license. We checked this carefully with the Foundation's lawyer and we believe this is the correct approach. Essentially, all code in the project is now made available by the LLVM project under our new license, so you will see that the license headers include that license only. Some of our contributors have contributed code under our old license, and accordingly, we have retained a copy of our old license notice in the top-level files in each project and repository. llvm-svn: 351636
487 lines
14 KiB
C++
487 lines
14 KiB
C++
//===-- AVRAsmBackend.cpp - AVR Asm Backend ------------------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the AVRAsmBackend class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AVRAsmBackend.h"
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#include "MCTargetDesc/AVRFixupKinds.h"
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#include "MCTargetDesc/AVRMCTargetDesc.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCDirectives.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCFixupKindInfo.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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// FIXME: we should be doing checks to make sure asm operands
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// are not out of bounds.
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namespace adjust {
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using namespace llvm;
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void signed_width(unsigned Width, uint64_t Value, std::string Description,
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const MCFixup &Fixup, MCContext *Ctx = nullptr) {
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if (!isIntN(Width, Value)) {
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std::string Diagnostic = "out of range " + Description;
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int64_t Min = minIntN(Width);
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int64_t Max = maxIntN(Width);
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Diagnostic += " (expected an integer in the range " + std::to_string(Min) +
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" to " + std::to_string(Max) + ")";
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if (Ctx) {
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Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
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} else {
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llvm_unreachable(Diagnostic.c_str());
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}
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}
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}
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void unsigned_width(unsigned Width, uint64_t Value, std::string Description,
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const MCFixup &Fixup, MCContext *Ctx = nullptr) {
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if (!isUIntN(Width, Value)) {
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std::string Diagnostic = "out of range " + Description;
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int64_t Max = maxUIntN(Width);
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Diagnostic += " (expected an integer in the range 0 to " +
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std::to_string(Max) + ")";
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if (Ctx) {
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Ctx->reportFatalError(Fixup.getLoc(), Diagnostic);
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} else {
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llvm_unreachable(Diagnostic.c_str());
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}
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}
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}
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/// Adjusts the value of a branch target before fixup application.
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void adjustBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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// We have one extra bit of precision because the value is rightshifted by
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// one.
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unsigned_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
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// Rightshifts the value by one.
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AVR::fixups::adjustBranchTarget(Value);
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}
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/// Adjusts the value of a relative branch target before fixup application.
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void adjustRelativeBranch(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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// We have one extra bit of precision because the value is rightshifted by
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// one.
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signed_width(Size + 1, Value, std::string("branch target"), Fixup, Ctx);
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Value -= 2;
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// Rightshifts the value by one.
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AVR::fixups::adjustBranchTarget(Value);
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}
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/// 22-bit absolute fixup.
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///
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/// Resolves to:
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/// 1001 kkkk 010k kkkk kkkk kkkk 111k kkkk
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///
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/// Offset of 0 (so the result is left shifted by 3 bits before application).
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void fixup_call(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustBranch(Size, Fixup, Value, Ctx);
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auto top = Value & (0xf00000 << 6); // the top four bits
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auto middle = Value & (0x1ffff << 5); // the middle 13 bits
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auto bottom = Value & 0x1f; // end bottom 5 bits
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Value = (top << 6) | (middle << 3) | (bottom << 0);
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}
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/// 7-bit PC-relative fixup.
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///
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/// Resolves to:
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/// 0000 00kk kkkk k000
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/// Offset of 0 (so the result is left shifted by 3 bits before application).
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void fixup_7_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustRelativeBranch(Size, Fixup, Value, Ctx);
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// Because the value may be negative, we must mask out the sign bits
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Value &= 0x7f;
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}
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/// 12-bit PC-relative fixup.
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/// Yes, the fixup is 12 bits even though the name says otherwise.
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///
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/// Resolves to:
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/// 0000 kkkk kkkk kkkk
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/// Offset of 0 (so the result isn't left-shifted before application).
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void fixup_13_pcrel(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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adjustRelativeBranch(Size, Fixup, Value, Ctx);
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// Because the value may be negative, we must mask out the sign bits
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Value &= 0xfff;
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}
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/// 6-bit fixup for the immediate operand of the ADIW family of
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/// instructions.
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///
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/// Resolves to:
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/// 0000 0000 kk00 kkkk
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void fixup_6_adiw(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(6, Value, std::string("immediate"), Fixup, Ctx);
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Value = ((Value & 0x30) << 2) | (Value & 0x0f);
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}
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/// 5-bit port number fixup on the SBIC family of instructions.
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///
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/// Resolves to:
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/// 0000 0000 AAAA A000
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void fixup_port5(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(5, Value, std::string("port number"), Fixup, Ctx);
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Value &= 0x1f;
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Value <<= 3;
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}
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/// 6-bit port number fixup on the `IN` family of instructions.
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///
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/// Resolves to:
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/// 1011 0AAd dddd AAAA
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void fixup_port6(const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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unsigned_width(6, Value, std::string("port number"), Fixup, Ctx);
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Value = ((Value & 0x30) << 5) | (Value & 0x0f);
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}
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/// Adjusts a program memory address.
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/// This is a simple right-shift.
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void pm(uint64_t &Value) {
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Value >>= 1;
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}
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/// Fixups relating to the LDI instruction.
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namespace ldi {
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/// Adjusts a value to fix up the immediate of an `LDI Rd, K` instruction.
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///
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/// Resolves to:
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/// 0000 KKKK 0000 KKKK
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/// Offset of 0 (so the result isn't left-shifted before application).
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void fixup(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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uint64_t upper = Value & 0xf0;
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uint64_t lower = Value & 0x0f;
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Value = (upper << 4) | lower;
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}
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void neg(uint64_t &Value) { Value *= -1; }
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void lo8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value &= 0xff;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void hi8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff00) >> 8;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void hh8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff0000) >> 16;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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void ms8(unsigned Size, const MCFixup &Fixup, uint64_t &Value,
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MCContext *Ctx = nullptr) {
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Value = (Value & 0xff000000) >> 24;
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ldi::fixup(Size, Fixup, Value, Ctx);
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}
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} // end of ldi namespace
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} // end of adjust namespace
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namespace llvm {
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// Prepare value for the target space for it
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void AVRAsmBackend::adjustFixupValue(const MCFixup &Fixup,
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const MCValue &Target,
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uint64_t &Value,
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MCContext *Ctx) const {
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// The size of the fixup in bits.
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uint64_t Size = AVRAsmBackend::getFixupKindInfo(Fixup.getKind()).TargetSize;
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unsigned Kind = Fixup.getKind();
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// Parsed LLVM-generated temporary labels are already
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// adjusted for instruction size, but normal labels aren't.
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//
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// To handle both cases, we simply un-adjust the temporary label
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// case so it acts like all other labels.
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if (const MCSymbolRefExpr *A = Target.getSymA()) {
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if (A->getSymbol().isTemporary())
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Value += 2;
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}
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switch (Kind) {
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default:
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llvm_unreachable("unhandled fixup");
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case AVR::fixup_7_pcrel:
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adjust::fixup_7_pcrel(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_13_pcrel:
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adjust::fixup_13_pcrel(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_call:
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adjust::fixup_call(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ldi:
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adjust::ldi::fixup(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_lo8_ldi:
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adjust::ldi::lo8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_lo8_ldi_pm:
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case AVR::fixup_lo8_ldi_gs:
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adjust::pm(Value);
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adjust::ldi::lo8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hi8_ldi:
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adjust::ldi::hi8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hi8_ldi_pm:
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case AVR::fixup_hi8_ldi_gs:
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adjust::pm(Value);
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adjust::ldi::hi8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hh8_ldi:
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case AVR::fixup_hh8_ldi_pm:
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if (Kind == AVR::fixup_hh8_ldi_pm) adjust::pm(Value);
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adjust::ldi::hh8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ms8_ldi:
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adjust::ldi::ms8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_lo8_ldi_neg:
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case AVR::fixup_lo8_ldi_pm_neg:
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if (Kind == AVR::fixup_lo8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::lo8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hi8_ldi_neg:
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case AVR::fixup_hi8_ldi_pm_neg:
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if (Kind == AVR::fixup_hi8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::hi8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_hh8_ldi_neg:
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case AVR::fixup_hh8_ldi_pm_neg:
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if (Kind == AVR::fixup_hh8_ldi_pm_neg) adjust::pm(Value);
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adjust::ldi::neg(Value);
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adjust::ldi::hh8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_ms8_ldi_neg:
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adjust::ldi::neg(Value);
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adjust::ldi::ms8(Size, Fixup, Value, Ctx);
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break;
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case AVR::fixup_16:
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adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
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Value &= 0xffff;
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break;
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case AVR::fixup_16_pm:
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Value >>= 1; // Flash addresses are always shifted.
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adjust::unsigned_width(16, Value, std::string("port number"), Fixup, Ctx);
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Value &= 0xffff;
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break;
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case AVR::fixup_6_adiw:
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adjust::fixup_6_adiw(Fixup, Value, Ctx);
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break;
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case AVR::fixup_port5:
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adjust::fixup_port5(Fixup, Value, Ctx);
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break;
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case AVR::fixup_port6:
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adjust::fixup_port6(Fixup, Value, Ctx);
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break;
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// Fixups which do not require adjustments.
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case FK_Data_1:
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case FK_Data_2:
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case FK_Data_4:
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case FK_Data_8:
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break;
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case FK_GPRel_4:
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llvm_unreachable("don't know how to adjust this fixup");
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break;
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}
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}
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std::unique_ptr<MCObjectTargetWriter>
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AVRAsmBackend::createObjectTargetWriter() const {
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return createAVRELFObjectWriter(MCELFObjectTargetWriter::getOSABI(OSType));
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}
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void AVRAsmBackend::applyFixup(const MCAssembler &Asm, const MCFixup &Fixup,
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const MCValue &Target,
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MutableArrayRef<char> Data, uint64_t Value,
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bool IsResolved,
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const MCSubtargetInfo *STI) const {
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adjustFixupValue(Fixup, Target, Value, &Asm.getContext());
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if (Value == 0)
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return; // Doesn't change encoding.
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MCFixupKindInfo Info = getFixupKindInfo(Fixup.getKind());
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// The number of bits in the fixup mask
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auto NumBits = Info.TargetSize + Info.TargetOffset;
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auto NumBytes = (NumBits / 8) + ((NumBits % 8) == 0 ? 0 : 1);
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// Shift the value into position.
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Value <<= Info.TargetOffset;
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unsigned Offset = Fixup.getOffset();
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assert(Offset + NumBytes <= Data.size() && "Invalid fixup offset!");
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// For each byte of the fragment that the fixup touches, mask in the
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// bits from the fixup value.
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for (unsigned i = 0; i < NumBytes; ++i) {
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uint8_t mask = (((Value >> (i * 8)) & 0xff));
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Data[Offset + i] |= mask;
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}
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}
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MCFixupKindInfo const &AVRAsmBackend::getFixupKindInfo(MCFixupKind Kind) const {
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// NOTE: Many AVR fixups work on sets of non-contignous bits. We work around
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// this by saying that the fixup is the size of the entire instruction.
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const static MCFixupKindInfo Infos[AVR::NumTargetFixupKinds] = {
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// This table *must* be in same the order of fixup_* kinds in
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// AVRFixupKinds.h.
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//
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// name offset bits flags
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{"fixup_32", 0, 32, 0},
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{"fixup_7_pcrel", 3, 7, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_13_pcrel", 0, 12, MCFixupKindInfo::FKF_IsPCRel},
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{"fixup_16", 0, 16, 0},
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{"fixup_16_pm", 0, 16, 0},
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{"fixup_ldi", 0, 8, 0},
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{"fixup_lo8_ldi", 0, 8, 0},
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{"fixup_hi8_ldi", 0, 8, 0},
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{"fixup_hh8_ldi", 0, 8, 0},
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{"fixup_ms8_ldi", 0, 8, 0},
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{"fixup_lo8_ldi_neg", 0, 8, 0},
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{"fixup_hi8_ldi_neg", 0, 8, 0},
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{"fixup_hh8_ldi_neg", 0, 8, 0},
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{"fixup_ms8_ldi_neg", 0, 8, 0},
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{"fixup_lo8_ldi_pm", 0, 8, 0},
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{"fixup_hi8_ldi_pm", 0, 8, 0},
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{"fixup_hh8_ldi_pm", 0, 8, 0},
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{"fixup_lo8_ldi_pm_neg", 0, 8, 0},
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{"fixup_hi8_ldi_pm_neg", 0, 8, 0},
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{"fixup_hh8_ldi_pm_neg", 0, 8, 0},
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{"fixup_call", 0, 22, 0},
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{"fixup_6", 0, 16, 0}, // non-contiguous
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{"fixup_6_adiw", 0, 6, 0},
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{"fixup_lo8_ldi_gs", 0, 8, 0},
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{"fixup_hi8_ldi_gs", 0, 8, 0},
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{"fixup_8", 0, 8, 0},
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{"fixup_8_lo8", 0, 8, 0},
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{"fixup_8_hi8", 0, 8, 0},
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{"fixup_8_hlo8", 0, 8, 0},
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{"fixup_diff8", 0, 8, 0},
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{"fixup_diff16", 0, 16, 0},
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{"fixup_diff32", 0, 32, 0},
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{"fixup_lds_sts_16", 0, 16, 0},
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{"fixup_port6", 0, 16, 0}, // non-contiguous
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{"fixup_port5", 3, 5, 0},
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};
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if (Kind < FirstTargetFixupKind)
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return MCAsmBackend::getFixupKindInfo(Kind);
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assert(unsigned(Kind - FirstTargetFixupKind) < getNumFixupKinds() &&
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"Invalid kind!");
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return Infos[Kind - FirstTargetFixupKind];
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}
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bool AVRAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count) const {
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// If the count is not 2-byte aligned, we must be writing data into the text
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// section (otherwise we have unaligned instructions, and thus have far
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// bigger problems), so just write zeros instead.
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assert((Count % 2) == 0 && "NOP instructions must be 2 bytes");
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OS.write_zeros(Count);
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return true;
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}
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bool AVRAsmBackend::shouldForceRelocation(const MCAssembler &Asm,
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const MCFixup &Fixup,
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const MCValue &Target) {
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switch ((unsigned) Fixup.getKind()) {
|
|
default: return false;
|
|
// Fixups which should always be recorded as relocations.
|
|
case AVR::fixup_7_pcrel:
|
|
case AVR::fixup_13_pcrel:
|
|
case AVR::fixup_call:
|
|
return true;
|
|
}
|
|
}
|
|
|
|
MCAsmBackend *createAVRAsmBackend(const Target &T, const MCSubtargetInfo &STI,
|
|
const MCRegisterInfo &MRI,
|
|
const llvm::MCTargetOptions &TO) {
|
|
return new AVRAsmBackend(STI.getTargetTriple().getOS());
|
|
}
|
|
|
|
} // end of namespace llvm
|
|
|