Matt Arsenault b10fa8df3f AMDGPU/GlobalISel: Fix bit count ops for non-power-of-2 types ...

llvm-svn: 354587

2019-02-21 15:22:20 +00:00

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AArch64

Add skipFunction to PostRA machine sinking pass.

2019-02-21 02:11:06 +00:00

AMDGPU

AMDGPU/GlobalISel: Fix bit count ops for non-power-of-2 types

2019-02-21 15:22:20 +00:00

ARC

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ARM

[ARM GlobalISel] Support G_FRAME_INDEX for Thumb2

2019-02-21 13:00:02 +00:00

AVR

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BPF

[BPF] make test case reloc-btf.ll tolerable for old compilers

2019-02-20 00:22:19 +00:00

Generic

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Hexagon

[Hexagon] Split vector pairs for ISD::SIGN_EXTEND and ISD::ZERO_EXTEND

2019-02-20 15:05:19 +00:00

Inputs

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Lanai

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Mips

[MIPS MSA] Avoid some DAG combines for vector shifts

2019-02-20 13:42:44 +00:00

MIR

[X86] Add FPCW as an implicit use on floating point load instructions.

2019-02-08 20:50:09 +00:00

MSP430

Enable integrated assembler on MSP430 by default.

2019-02-05 18:01:45 +00:00

NVPTX

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PowerPC

[PowerPC] exploit P9 instruction maddld.

2019-02-20 02:30:06 +00:00

RISCV

[RISCV] Re-organise calling convention tests

2019-02-19 13:47:19 +00:00

SPARC

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SystemZ

Recommit "[SystemZ] Do not emit VEXTEND or VROUND nodes without vector support."

2019-02-15 19:13:55 +00:00

Thumb

Revert 354564: [ARM] Add some missing thumb1 opcodes to enable peephole optimisation of CMPs

2019-02-21 11:03:13 +00:00

Thumb2

[ARM] Ensure we update the correct flags in the peephole optimiser

2019-02-14 11:09:24 +00:00

WebAssembly

[WebAssembly] Default to something reasonable in WebAssemblyAddMissingPrototypes

2019-02-21 03:27:00 +00:00

WinCFGuard

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WinEH

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X86

[X86] Add test cases to show missed opportunities to remove AND mask from BTC/BTS/BTR instructions when LHS of AND has known zeros.

2019-02-20 21:35:05 +00:00

XCore

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