cf78715cae
Ooops. It constructs codegen infra and provide only basic code to generate first add instruction successfully. Differential Revision: https://reviews.llvm.org/D112206
34 lines
802 B
LLVM
34 lines
802 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -verify-machineinstrs -csky-no-aliases -mattr=+e2 < %s -mtriple=csky | FileCheck %s
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define i32 @addRR(i32 %x, i32 %y) {
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; CHECK-LABEL: addRR:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addu32 a0, a1, a0
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; CHECK-NEXT: rts32
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entry:
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%add = add nsw i32 %y, %x
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ret i32 %add
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}
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define i32 @addRI(i32 %x) {
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; CHECK-LABEL: addRI:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: addi32 a0, a0, 10
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; CHECK-NEXT: rts32
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entry:
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%add = add nsw i32 %x, 10
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ret i32 %add
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}
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define i32 @addRI_X(i32 %x) {
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; CHECK-LABEL: addRI_X:
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; CHECK: # %bb.0: # %entry
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; CHECK-NEXT: movi32 a1, 4097
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; CHECK-NEXT: addu32 a0, a0, a1
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; CHECK-NEXT: rts32
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entry:
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%add = add nsw i32 %x, 4097
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ret i32 %add
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}
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