Simon Pilgrim aeb3c772d3 [X86] Add shift by splat modulo amount vector tests ...

Shows failure to fold zero_extend_vector_inreg(and(x, c)) -> bitcast(and(x,c')) when we're only demanding the 0'th extended element, such as with the SSE variable shift ops.

2021-11-16 20:46:17 +00:00

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AArch64

[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

2021-11-16 16:25:16 +00:00

AMDGPU

[amdgpu] Don't crash on empty global ctor/dtor

2021-11-16 14:36:08 +00:00

ARC

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ARM

[ARM] implement support for TLS register based stack protector

2021-11-09 18:19:47 +01:00

AVR

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BPF

BPF: change btf_type_tag BTF output format

2021-11-09 11:34:25 -08:00

CSKY

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Generic

[asm] Correctly handle special names in variants

2021-11-15 15:37:09 -05:00

Hexagon

[LiveIntervals] Update subranges in processTiedPairs

2021-11-11 12:24:59 +00:00

Inputs

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Lanai

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M68k

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Mips

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MIR

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

2021-11-07 15:06:54 +00:00

MSP430

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NVPTX

[NVPTX] Add imm variants for surface and texture instructions

2021-11-10 19:05:03 +03:00

PowerPC

[PowerPC] PPC backend optimization on conditional trap intrustions

2021-11-16 13:11:57 -06:00

RISCV

[RISCV] Override TargetLowering::hasAndNot for Zbb.

2021-11-15 18:44:07 -08:00

SPARC

[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers

2021-11-14 19:59:52 +01:00

SystemZ

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Thumb

[TwoAddressInstructionPass] Update existing physreg live intervals

2021-11-05 21:20:30 +00:00

Thumb2

[SCEV] Canonicalize X - urem X, Y patterns

2021-11-16 11:59:21 -08:00

VE

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WebAssembly

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WinCFGuard

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WinEH

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X86

[X86] Add shift by splat modulo amount vector tests

2021-11-16 20:46:17 +00:00

XCore

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