Simon Pilgrim aeb3c772d3 [X86] Add shift by splat modulo amount vector tests ...

Shows failure to fold zero_extend_vector_inreg(and(x, c)) -> bitcast(and(x,c')) when we're only demanding the 0'th extended element, such as with the SSE variable shift ops.

2021-11-16 20:46:17 +00:00

..

AArch64

[AArch64] Fix TypeSize->uint64_t implicit conversion in AArch64ISelLowering::hasAndNot

2021-11-16 16:25:16 +00:00

AMDGPU

[amdgpu] Don't crash on empty global ctor/dtor

2021-11-16 14:36:08 +00:00

ARC

[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE

2021-09-10 13:04:08 -07:00

ARM

[ARM] implement support for TLS register based stack protector

2021-11-09 18:19:47 +01:00

AVR

[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation

2021-10-11 15:28:31 -07:00

BPF

BPF: change btf_type_tag BTF output format

2021-11-09 11:34:25 -08:00

CSKY

[CSKY] First patch to construct codegen infra and generate first add instruction

2021-11-01 10:06:56 +08:00

Generic

[asm] Correctly handle special names in variants

2021-11-15 15:37:09 -05:00

Hexagon

[LiveIntervals] Update subranges in processTiedPairs

2021-11-11 12:24:59 +00:00

Inputs

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Lanai

[Lanai] implement wide immediate support

2021-09-10 10:54:43 +00:00

M68k

[M68k][test] Migrate the remaining fixup and relaxation tests

2021-09-04 16:27:13 -07:00

Mips

[SelectionDAG] Optimize expansion for rotates/funnel shifts

2021-11-02 11:38:25 +00:00

MIR

[X86] Update RET/LRET instruction to use the same naming convention as IRET (PR36876). NFC

2021-11-07 15:06:54 +00:00

MSP430

[llvm-readobj] Support dumping of MSP430 ELF attributes

2021-09-28 00:56:11 +03:00

NVPTX

[NVPTX] Add imm variants for surface and texture instructions

2021-11-10 19:05:03 +03:00

PowerPC

[PowerPC] PPC backend optimization on conditional trap intrustions

2021-11-16 13:11:57 -06:00

RISCV

[RISCV] Override TargetLowering::hasAndNot for Zbb.

2021-11-15 18:44:07 -08:00

SPARC

[SPARC] Zero-extend the operands when doing UMULO on 64-bit integers

2021-11-14 19:59:52 +01:00

SystemZ

[SystemZ] Improvement of emitMemMemWrapper()

2021-10-26 17:03:01 +02:00

Thumb

[TwoAddressInstructionPass] Update existing physreg live intervals

2021-11-05 21:20:30 +00:00

Thumb2

[SCEV] Canonicalize X - urem X, Y patterns

2021-11-16 11:59:21 -08:00

VE

[VE][NFC] correct bitmasking in popcnt expansion test

2021-10-25 13:55:58 +02:00

WebAssembly

[WebAssembly] Add prototype relaxed float to int trunc instructions

2021-10-28 14:01:53 -07:00

WinCFGuard

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WinEH

Fix SEH table addresses for Windows

2021-08-20 22:32:12 +03:00

X86

[X86] Add shift by splat modulo amount vector tests

2021-11-16 20:46:17 +00:00

XCore

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