Jay Foad bdaa181007 [TwoAddressInstructionPass] Update existing physreg live intervals ...

In TwoAddressInstructionPass::processTiedPairs with
-early-live-intervals, update any preexisting physreg live intervals,
as well as virtreg live intervals. By default (without
-precompute-phys-liveness) physreg live intervals only exist for
registers that are live-in to some basic block.

Differential Revision: https://reviews.llvm.org/D113191

2021-11-05 21:20:30 +00:00

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2007-01-31-RegInfoAssert.ll

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2007-02-02-JoinIntervalsCrash.ll

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2007-05-05-InvalidPushPop.ll

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2009-06-18-ThumbCommuteMul.ll

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2009-07-20-TwoAddrBug.ll

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2009-07-27-PEIAssert.ll

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2009-08-12-ConstIslandAssert.ll

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2009-08-12-RegInfoAssert.ll

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2009-08-20-ISelBug.ll

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2009-12-17-pre-regalloc-taildup.ll

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2010-06-18-SibCallCrash.ll

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2010-07-01-FuncAlign.ll

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2010-07-15-debugOrdering.ll

OpaquePtr: Update more tests to use typed sret

2020-11-20 20:08:43 -05:00

2011-05-11-DAGLegalizer.ll

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2011-06-16-NoGPRs.ll

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2011-EpilogueBug.ll

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2012-04-26-M0ISelBug.ll

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2014-06-10-thumb1-ldst-opt-bug.ll

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addr-modes.ll

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and_neg.ll

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asmprinter-bug.ll

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barrier.ll

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bic_imm.ll

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branchless-cmp.ll

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callee_save.ll

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cmp-add-fold.ll

[ARM] Regenerate some test checks. NFC

2021-03-24 15:34:34 +00:00

cmp-and-fold.ll

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cmp-fold.ll

[ARM] Regenerate some test checks. NFC

2021-03-24 15:34:34 +00:00

constants.ll

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consthoist-few-dependents.ll

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consthoist-imm8-costs-1.ll

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consthoist-physical-addr.ll

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copy_thumb.ll

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cortex-m0-unaligned-access.ll

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DbgValueOtherTargets.test

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dyn-stackalloc.ll

Revert "Allow rematerialization of virtual reg uses"

2021-09-24 10:26:11 -07:00

emergency-spill-slot.ll

[TwoAddressInstructionPass] Update existing physreg live intervals

2021-11-05 21:20:30 +00:00

fastcc.ll

Revert "[NFC] remove explicit default value for strboolattr attribute in tests"

2021-05-24 19:43:40 +02:00

fpconv.ll

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fpow.ll

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frame_thumb.ll

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frame-access.ll

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high-reg-clobber.mir

[NFC] Adding test for clobbering of high registers in Thumb

2021-06-28 13:44:44 +01:00

i8-phi-ext.ll

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iabs-vector.ll

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iabs.ll

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inline-asm-i-constraint-i1.ll

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inlineasm-imm-thumb.ll

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inlineasm-thumb.ll

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ispositive.ll

[ARM] Regenerate some test checks. NFC

2021-03-24 15:34:34 +00:00

large-fn-switch.ll

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large-stack.ll

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ldm-merge-call.ll

Revert "[NFC] remove explicit default value for strboolattr attribute in tests"

2021-05-24 19:43:40 +02:00

ldm-merge-struct.ll

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ldm-stm-base-materialization-thumb2.ll

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ldm-stm-base-materialization.ll

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ldm-stm-postinc.ll

[ARM] Make sure we don't transform unaligned store to stm on Thumb1.

2021-06-21 14:32:42 -07:00

ldr_ext.ll

[ARM] Use lrdsb for more thumb1 loads.

2021-03-17 15:29:02 +00:00

ldr_frame.ll

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lit.local.cfg

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litpoolremat.ll

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long_shift.ll

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long-setcc.ll

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long.ll

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machine-cse-deadreg.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

machine-cse-physreg.mir

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mature-mc-support.ll

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mul.ll

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mvn.ll

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opt-phis.mir

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optionaldef-scheduling.ll

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peephole-cmp.mir

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peephole-mi.mir

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pop.ll

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pr35836_2.ll

[TwoAddressInstructionPass] Improve the SrcRegMap and DstRegMap computation

2021-10-11 15:28:31 -07:00

pr35836.ll

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pr42760.ll

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PR17309.ll

Revert "[NFC] remove explicit default value for strboolattr attribute in tests"

2021-05-24 19:43:40 +02:00

PR35481.ll

[ARM] Change a couple of instances of LiveRegs.contains to !LiveRegs.available

2021-08-10 09:53:26 +01:00

PR36658.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

push.ll

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ragreedy-implicit-def.ll

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rev.ll

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scheduler-clone-cpsr-def.ll

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segmented-stacks-dynamic.ll

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segmented-stacks.ll

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select.ll

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shift-and.ll

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sjljehprepare-lower-vector.ll

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srem-seteq-illegal-types.ll

Support {S,U}REMEqFold before legalization

2021-04-01 01:35:41 +03:00

stack_guard_remat.ll

Revert "[NFC] remove explicit default value for strboolattr attribute in tests"

2021-05-24 19:43:40 +02:00

stack-access.ll

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stack-coloring-without-frame-ptr.ll

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stack-frame.ll

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stack-mis-alignment.ll

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stm-deprecated.ll

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stm-merge.ll

Revert "[NFC] remove explicit default value for strboolattr attribute in tests"

2021-05-24 19:43:40 +02:00

stm-scavenging.ll

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tbb-reuse.mir

CodeGen: Print/parse LLTs in MachineMemOperands

2021-06-30 16:54:13 -04:00

thumb1-cmp.ll

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thumb-imm.ll

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thumb-ldm.ll

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thumb-shrink-wrapping.ll

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trap.ll

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triple.ll

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tst_teq.ll

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umulo-32-legalisation-lowering.ll

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umulo-128-legalisation-lowering.ll

Do not generate calls to the 128-bit function __multi3() on 32-bit ARM

2021-06-11 11:45:21 +01:00

unord.ll

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urem-seteq-illegal-types.ll

[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)

2021-09-07 15:42:43 +08:00

uxth.ll

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vargs.ll

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