facff468b6
GPR uses argument registers as the first group of registers to allocate. This patch uses vector argument registers, v8 to v23, as the first group to allocate. Differential Revision: https://reviews.llvm.org/D111304
60 lines
1.7 KiB
LLVM
60 lines
1.7 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -mattr=+d -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32IFD %s
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define double @test(double %a) nounwind {
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; RV32IFD-LABEL: test:
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; RV32IFD: # %bb.0:
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; RV32IFD-NEXT: ret
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ret double %a
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}
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; This previously failed complaining of multiple vreg defs due to an ABI
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; lowering issue.
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define i32 @main() nounwind {
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; RV32IFD-LABEL: main:
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; RV32IFD: # %bb.0: # %entry
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; RV32IFD-NEXT: addi sp, sp, -16
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; RV32IFD-NEXT: sw ra, 12(sp) # 4-byte Folded Spill
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; RV32IFD-NEXT: lui a1, 262144
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; RV32IFD-NEXT: mv a0, zero
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; RV32IFD-NEXT: call test@plt
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; RV32IFD-NEXT: sw a0, 0(sp)
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; RV32IFD-NEXT: sw a1, 4(sp)
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; RV32IFD-NEXT: fld ft0, 0(sp)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI1_0)
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; RV32IFD-NEXT: fld ft1, %lo(.LCPI1_0)(a0)
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; RV32IFD-NEXT: lui a0, %hi(.LCPI1_1)
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; RV32IFD-NEXT: fld ft2, %lo(.LCPI1_1)(a0)
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; RV32IFD-NEXT: flt.d a0, ft0, ft1
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; RV32IFD-NEXT: not a0, a0
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; RV32IFD-NEXT: flt.d a1, ft2, ft0
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; RV32IFD-NEXT: xori a1, a1, 1
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; RV32IFD-NEXT: and a0, a0, a1
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; RV32IFD-NEXT: bnez a0, .LBB1_2
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; RV32IFD-NEXT: # %bb.1: # %if.then
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; RV32IFD-NEXT: call abort@plt
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; RV32IFD-NEXT: .LBB1_2: # %if.end
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; RV32IFD-NEXT: mv a0, zero
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; RV32IFD-NEXT: call exit@plt
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entry:
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%call = call double @test(double 2.000000e+00)
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%cmp = fcmp olt double %call, 2.400000e-01
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%cmp2 = fcmp ogt double %call, 2.600000e-01
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%or.cond = or i1 %cmp, %cmp2
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br i1 %or.cond, label %if.then, label %if.end
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if.then:
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call void @abort()
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unreachable
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if.end:
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call void @exit(i32 0)
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unreachable
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}
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declare void @abort()
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declare void @exit(i32)
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