facff468b6
GPR uses argument registers as the first group of registers to allocate. This patch uses vector argument registers, v8 to v23, as the first group to allocate. Differential Revision: https://reviews.llvm.org/D111304
86 lines
2.6 KiB
LLVM
86 lines
2.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV32 %s
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; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
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; RUN: | FileCheck -check-prefix=RV64 %s
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define fastcc i32 @callee(<16 x i32> %A) nounwind {
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; RV32-LABEL: callee:
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; RV32: # %bb.0:
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; RV32-NEXT: ret
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;
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; RV64-LABEL: callee:
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; RV64: # %bb.0:
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; RV64-NEXT: ret
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%B = extractelement <16 x i32> %A, i32 0
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ret i32 %B
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}
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; With the fastcc, arguments will be passed by a0-a7 and t2-t6.
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; The rest will be pushed on the stack.
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define i32 @caller(<16 x i32> %A) nounwind {
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; RV32-LABEL: caller:
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; RV32: # %bb.0:
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; RV32-NEXT: addi sp, sp, -32
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; RV32-NEXT: sw ra, 28(sp) # 4-byte Folded Spill
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; RV32-NEXT: sw s0, 24(sp) # 4-byte Folded Spill
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; RV32-NEXT: lw t0, 0(a0)
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; RV32-NEXT: lw a1, 4(a0)
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; RV32-NEXT: lw a2, 8(a0)
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; RV32-NEXT: lw a3, 12(a0)
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; RV32-NEXT: lw a4, 16(a0)
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; RV32-NEXT: lw a5, 20(a0)
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; RV32-NEXT: lw a6, 24(a0)
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; RV32-NEXT: lw a7, 28(a0)
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; RV32-NEXT: lw t2, 32(a0)
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; RV32-NEXT: lw t3, 36(a0)
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; RV32-NEXT: lw t4, 40(a0)
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; RV32-NEXT: lw t5, 44(a0)
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; RV32-NEXT: lw t6, 48(a0)
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; RV32-NEXT: lw t1, 52(a0)
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; RV32-NEXT: lw s0, 56(a0)
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; RV32-NEXT: lw a0, 60(a0)
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; RV32-NEXT: sw a0, 8(sp)
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; RV32-NEXT: sw s0, 4(sp)
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; RV32-NEXT: sw t1, 0(sp)
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; RV32-NEXT: mv a0, t0
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; RV32-NEXT: call callee@plt
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; RV32-NEXT: lw s0, 24(sp) # 4-byte Folded Reload
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; RV32-NEXT: lw ra, 28(sp) # 4-byte Folded Reload
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; RV32-NEXT: addi sp, sp, 32
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; RV32-NEXT: ret
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;
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; RV64-LABEL: caller:
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; RV64: # %bb.0:
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; RV64-NEXT: addi sp, sp, -48
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; RV64-NEXT: sd ra, 40(sp) # 8-byte Folded Spill
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; RV64-NEXT: sd s0, 32(sp) # 8-byte Folded Spill
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; RV64-NEXT: ld t0, 0(a0)
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; RV64-NEXT: ld a1, 8(a0)
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; RV64-NEXT: ld a2, 16(a0)
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; RV64-NEXT: ld a3, 24(a0)
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; RV64-NEXT: ld a4, 32(a0)
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; RV64-NEXT: ld a5, 40(a0)
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; RV64-NEXT: ld a6, 48(a0)
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; RV64-NEXT: ld a7, 56(a0)
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; RV64-NEXT: ld t2, 64(a0)
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; RV64-NEXT: ld t3, 72(a0)
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; RV64-NEXT: ld t4, 80(a0)
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; RV64-NEXT: ld t5, 88(a0)
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; RV64-NEXT: ld t6, 96(a0)
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; RV64-NEXT: ld t1, 104(a0)
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; RV64-NEXT: ld s0, 112(a0)
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; RV64-NEXT: ld a0, 120(a0)
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; RV64-NEXT: sd a0, 16(sp)
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; RV64-NEXT: sd s0, 8(sp)
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; RV64-NEXT: sd t1, 0(sp)
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; RV64-NEXT: mv a0, t0
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; RV64-NEXT: call callee@plt
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; RV64-NEXT: ld s0, 32(sp) # 8-byte Folded Reload
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; RV64-NEXT: ld ra, 40(sp) # 8-byte Folded Reload
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; RV64-NEXT: addi sp, sp, 48
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; RV64-NEXT: ret
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%C = call fastcc i32 @callee(<16 x i32> %A)
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ret i32 %C
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}
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