caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
b20da5117fb66e7f9bcb56cb14af86dcafe2ee9a
clang-p2996/llvm/test/CodeGen/Thumb2/LowOverheadLoops/matrix.mir
David Green 9cb8f4d1ad [ARM] Add a tail-predication loop predicate register 
The semantics of tail predication loops means that the value of LR as an
instruction is executed determines the predicate. In other words:

mov r3, #3
DLSTP lr, r3        // Start tail predication, lr==3
VADD.s32 q0, q1, q2 // Lanes 0,1 and 2 are updated in q0.
mov lr, #1
VADD.s32 q0, q1, q2 // Only first lane is updated.

This means that the value of lr cannot be spilled and re-used in tail
predication regions without potentially altering the behaviour of the
program. More lanes than required could be stored, for example, and in
the case of a gather those lanes might not have been setup, leading to
alignment exceptions.

This patch adds a new lr predicate operand to MVE instructions in order
to keep a reference to the lr that they use as a tail predicate. It will
usually hold the zeroreg meaning not predicated, being set to the LR phi
value in the MVETPAndVPTOptimisationsPass. This will prevent it from
being spilled anywhere that it needs to be used.

A lot of tests needed updating.

Differential Revision: https://reviews.llvm.org/D107638
2021-09-02 13:42:58 +01:00

544 lines
29 KiB
YAML
Raw Blame History

# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=thumbv8.1m.main -mattr=+mve -run-pass=arm-low-overhead-loops %s -o - --verify-machineinstrs | FileCheck %s
# A decent sized test to handle a matrix, with scalar and vector low-overhead loops.
--- |
define dso_local arm_aapcs_vfpcc signext i16 @matrix_test(i32 %d, i32* nocapture %e, i16* nocapture readonly %k, i16* nocapture readonly %l) {
entry:
%cmp19.i = icmp sgt i32 %d, 0
br i1 %cmp19.i, label %for.body.i.preheader, label %c.exit.thread
for.body.i.preheader: ; preds = %entry
%start1 = call i32 @llvm.start.loop.iterations.i32(i32 %d)
br label %for.body.i
c.exit.thread: ; preds = %entry
%call169 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 0)
%conv270 = sext i16 %call169 to i32
br label %c.exit59
for.body.i: ; preds = %for.body.i, %for.body.i.preheader
%lsr.iv15 = phi i32* [ %e, %for.body.i.preheader ], [ %scevgep16, %for.body.i ]
%h.022.i = phi i16 [ %h.1.i, %for.body.i ], [ 0, %for.body.i.preheader ]
%f.020.i = phi i32 [ %f.1.i, %for.body.i ], [ undef, %for.body.i.preheader ]
%0 = phi i32 [ %start1, %for.body.i.preheader ], [ %2, %for.body.i ]
%1 = load i32, i32* %lsr.iv15, align 4
%add.i = add nsw i32 %1, %f.020.i
%cmp1.i = icmp sgt i32 %add.i, 0
%cmp3.i = icmp sgt i32 %1, 0
%f.1.i = select i1 %cmp1.i, i32 0, i32 %add.i
%narrow.i = and i1 %cmp3.i, %cmp1.i
%add6.i = zext i1 %narrow.i to i16
%h.1.i = add i16 %h.022.i, %add6.i
%scevgep16 = getelementptr i32, i32* %lsr.iv15, i32 1
%2 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %0, i32 1)
%3 = icmp ne i32 %2, 0
br i1 %3, label %for.body.i, label %c.exit
c.exit: ; preds = %for.body.i
%4 = icmp sgt i32 %d, 0
%phitmp = sext i16 %h.1.i to i32
%call1 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32)*)(i32 %phitmp)
%conv2 = sext i16 %call1 to i32
br i1 %4, label %for.cond4.preheader.us.preheader, label %c.exit59
for.cond4.preheader.us.preheader: ; preds = %c.exit
%n.rnd.up = add i32 %d, 3
%n.vec = and i32 %n.rnd.up, -4
%5 = shl i32 %d, 1
%6 = add i32 %n.vec, -4
%7 = lshr i32 %6, 2
%8 = add nuw nsw i32 %7, 1
%9 = shl i32 %7, 2
%10 = sub i32 %d, %9
br label %for.cond4.preheader.us
for.cond4.preheader.us: ; preds = %middle.block, %for.cond4.preheader.us.preheader
%lsr.iv7 = phi i16* [ %28, %middle.block ], [ %k, %for.cond4.preheader.us.preheader ]
%i.064.us = phi i32 [ %inc15.us, %middle.block ], [ 0, %for.cond4.preheader.us.preheader ]
%arrayidx12.us = getelementptr inbounds i32, i32* %e, i32 %i.064.us
%arrayidx12.promoted.us = load i32, i32* %arrayidx12.us, align 4
%11 = insertelement <4 x i32> <i32 undef, i32 0, i32 0, i32 0>, i32 %arrayidx12.promoted.us, i32 0
%start2 = call i32 @llvm.start.loop.iterations.i32(i32 %8)
br label %vector.body
vector.body: ; preds = %vector.body, %for.cond4.preheader.us
%lsr.iv10 = phi i16* [ %scevgep11, %vector.body ], [ %lsr.iv7, %for.cond4.preheader.us ]
%lsr.iv4 = phi i16* [ %scevgep5, %vector.body ], [ %l, %for.cond4.preheader.us ]
%vec.phi = phi <4 x i32> [ %11, %for.cond4.preheader.us ], [ %19, %vector.body ]
%12 = phi i32 [ %start2, %for.cond4.preheader.us ], [ %20, %vector.body ]
%13 = phi i32 [ %d, %for.cond4.preheader.us ], [ %15, %vector.body ]
%lsr.iv1012 = bitcast i16* %lsr.iv10 to <4 x i16>*
%lsr.iv46 = bitcast i16* %lsr.iv4 to <4 x i16>*
%14 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %13)
%15 = sub i32 %13, 4
%wide.masked.load = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv1012, i32 2, <4 x i1> %14, <4 x i16> undef)
%16 = sext <4 x i16> %wide.masked.load to <4 x i32>
%wide.masked.load76 = call <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>* %lsr.iv46, i32 2, <4 x i1> %14, <4 x i16> undef)
%17 = sext <4 x i16> %wide.masked.load76 to <4 x i32>
%18 = mul nsw <4 x i32> %17, %16
%19 = add <4 x i32> %18, %vec.phi
%scevgep5 = getelementptr i16, i16* %lsr.iv4, i32 4
%scevgep11 = getelementptr i16, i16* %lsr.iv10, i32 4
%20 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %12, i32 1)
%21 = icmp ne i32 %20, 0
br i1 %21, label %vector.body, label %middle.block
middle.block: ; preds = %vector.body
%vec.phi.lcssa = phi <4 x i32> [ %vec.phi, %vector.body ]
%.lcssa = phi <4 x i32> [ %19, %vector.body ]
%22 = call <4 x i1> @llvm.arm.mve.vctp32(i32 %10)
%23 = bitcast i16* %lsr.iv7 to i1*
%24 = select <4 x i1> %22, <4 x i32> %.lcssa, <4 x i32> %vec.phi.lcssa
%25 = call i32 @llvm.vector.reduce.add.v4i32(<4 x i32> %24)
%sunkaddr = mul i32 %i.064.us, 4
%26 = bitcast i32* %e to i8*
%sunkaddr17 = getelementptr inbounds i8, i8* %26, i32 %sunkaddr
%27 = bitcast i8* %sunkaddr17 to i32*
store i32 %25, i32* %27, align 4
%inc15.us = add nuw nsw i32 %i.064.us, 1
%scevgep9 = getelementptr i1, i1* %23, i32 %5
%28 = bitcast i1* %scevgep9 to i16*
%exitcond66 = icmp eq i32 %inc15.us, %d
br i1 %exitcond66, label %for.end16, label %for.cond4.preheader.us
for.end16: ; preds = %middle.block
%29 = icmp sgt i32 %d, 0
br i1 %29, label %for.body.i57.preheader, label %c.exit59
for.body.i57.preheader: ; preds = %for.end16
%start3 = call i32 @llvm.start.loop.iterations.i32(i32 %d)
br label %for.body.i57
for.body.i57: ; preds = %for.body.i57, %for.body.i57.preheader
%lsr.iv1 = phi i32* [ %e, %for.body.i57.preheader ], [ %scevgep, %for.body.i57 ]
%h.022.i44 = phi i16 [ %h.1.i54, %for.body.i57 ], [ 0, %for.body.i57.preheader ]
%f.020.i46 = phi i32 [ %f.1.i51, %for.body.i57 ], [ undef, %for.body.i57.preheader ]
%30 = phi i32 [ %start3, %for.body.i57.preheader ], [ %32, %for.body.i57 ]
%31 = load i32, i32* %lsr.iv1, align 4
%add.i48 = add nsw i32 %31, %f.020.i46
%cmp1.i49 = icmp sgt i32 %add.i48, 0
%cmp3.i50 = icmp sgt i32 %31, 0
%f.1.i51 = select i1 %cmp1.i49, i32 0, i32 %add.i48
%narrow.i52 = and i1 %cmp3.i50, %cmp1.i49
%add6.i53 = zext i1 %narrow.i52 to i16
%h.1.i54 = add i16 %h.022.i44, %add6.i53
%scevgep = getelementptr i32, i32* %lsr.iv1, i32 1
%32 = call i32 @llvm.loop.decrement.reg.i32.i32.i32(i32 %30, i32 1)
%33 = icmp ne i32 %32, 0
br i1 %33, label %for.body.i57, label %c.exit59.loopexit
c.exit59.loopexit: ; preds = %for.body.i57
%phitmp67 = sext i16 %h.1.i54 to i32
br label %c.exit59
c.exit59: ; preds = %c.exit59.loopexit, %for.end16, %c.exit, %c.exit.thread
%conv27173 = phi i32 [ %conv2, %for.end16 ], [ %conv2, %c.exit59.loopexit ], [ %conv2, %c.exit ], [ %conv270, %c.exit.thread ]
%h.0.lcssa.i58 = phi i32 [ 0, %for.end16 ], [ %phitmp67, %c.exit59.loopexit ], [ 0, %c.exit ], [ 0, %c.exit.thread ]
%call19 = tail call arm_aapcs_vfpcc signext i16 bitcast (i16 (...)* @crc16 to i16 (i32, i32)*)(i32 %h.0.lcssa.i58, i32 %conv27173)
ret i16 %call19
}
declare dso_local arm_aapcs_vfpcc signext i16 @crc16(...) local_unnamed_addr #0
declare <4 x i16> @llvm.masked.load.v4i16.p0v4i16(<4 x i16>*, i32 immarg, <4 x i1>, <4 x i16>) #1
declare i32 @llvm.vector.reduce.add.v4i32(<4 x i32>) #2
declare i32 @llvm.start.loop.iterations.i32(i32) #3
declare i32 @llvm.loop.decrement.reg.i32.i32.i32(i32, i32) #3
declare <4 x i1> @llvm.arm.mve.vctp32(i32) #4
...
---
name: matrix_test
alignment: 2
exposesReturnsTwice: false
legalized: false
regBankSelected: false
selected: false
failedISel: false
tracksRegLiveness: true
hasWinCFI: false
registers: []
liveins:
- { reg: '$r0', virtual-reg: '' }
- { reg: '$r1', virtual-reg: '' }
- { reg: '$r2', virtual-reg: '' }
- { reg: '$r3', virtual-reg: '' }
frameInfo:
isFrameAddressTaken: false
isReturnAddressTaken: false
hasStackMap: false
hasPatchPoint: false
stackSize: 32
offsetAdjustment: 0
maxAlignment: 4
adjustsStack: true
hasCalls: true
stackProtector: ''
maxCallFrameSize: 0
cvBytesOfCalleeSavedRegisters: 0
hasOpaqueSPAdjustment: false
hasVAStart: false
hasMustTailInVarArgFunc: false
localFrameSize: 0
savePoint: ''
restorePoint: ''
fixedStack: []
stack:
- { id: 0, name: '', type: spill-slot, offset: -4, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$lr', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 1, name: '', type: spill-slot, offset: -8, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r10', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 2, name: '', type: spill-slot, offset: -12, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r9', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 3, name: '', type: spill-slot, offset: -16, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r8', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 4, name: '', type: spill-slot, offset: -20, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r7', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 5, name: '', type: spill-slot, offset: -24, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r6', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 6, name: '', type: spill-slot, offset: -28, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r5', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
- { id: 7, name: '', type: spill-slot, offset: -32, size: 4, alignment: 4,
stack-id: default, callee-saved-register: '$r4', callee-saved-restored: true,
debug-info-variable: '', debug-info-expression: '', debug-info-location: '' }
callSites: []
constants: []
machineFunctionInfo: {}
body: |
; CHECK-LABEL: name: matrix_test
; CHECK: bb.0.entry:
; CHECK: successors: %bb.1(0x50000000), %bb.12(0x30000000)
; CHECK: liveins: $lr, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10
; CHECK: $sp = frame-setup t2STMDB_UPD $sp, 14 /* CC::al */, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
; CHECK: frame-setup CFI_INSTRUCTION def_cfa_offset 32
; CHECK: frame-setup CFI_INSTRUCTION offset $lr, -4
; CHECK: frame-setup CFI_INSTRUCTION offset $r10, -8
; CHECK: frame-setup CFI_INSTRUCTION offset $r9, -12
; CHECK: frame-setup CFI_INSTRUCTION offset $r8, -16
; CHECK: frame-setup CFI_INSTRUCTION offset $r7, -20
; CHECK: frame-setup CFI_INSTRUCTION offset $r6, -24
; CHECK: frame-setup CFI_INSTRUCTION offset $r5, -28
; CHECK: frame-setup CFI_INSTRUCTION offset $r4, -32
; CHECK: tCMPi8 renamable $r0, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: t2Bcc %bb.12, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.1.for.body.i.preheader:
; CHECK: successors: %bb.2(0x80000000)
; CHECK: liveins: $r0, $r1, $r2, $r3
; CHECK: $r5 = tMOVr killed $r2, 14 /* CC::al */, $noreg
; CHECK: $r8 = tMOVr killed $r3, 14 /* CC::al */, $noreg
; CHECK: $r4 = tMOVr $r1, 14 /* CC::al */, $noreg
; CHECK: renamable $r6, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = IMPLICIT_DEF
; CHECK: $r10 = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS killed renamable $r0
; CHECK: bb.2.for.body.i:
; CHECK: successors: %bb.2(0x7c000000), %bb.3(0x04000000)
; CHECK: liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10
; CHECK: renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv15)
; CHECK: renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 killed renamable $r3, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK: $r2 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
; CHECK: renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.2
; CHECK: bb.3.c.exit:
; CHECK: successors: %bb.4(0x50000000), %bb.14(0x30000000)
; CHECK: liveins: $r4, $r5, $r6, $r8, $r10
; CHECK: renamable $r0 = tSXTH killed renamable $r6, 14 /* CC::al */, $noreg
; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: t2CMPri $r10, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.14, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.4.for.cond4.preheader.us.preheader:
; CHECK: successors: %bb.5(0x80000000)
; CHECK: liveins: $r4, $r5, $r7, $r8, $r10, $r12
; CHECK: renamable $r0 = t2ADDri $r10, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r0 = t2BICri killed renamable $r0, 3, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r3 = t2LSLri $r10, 1, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $r0, dead $cpsr = tMOVi8 1, 14 /* CC::al */, $noreg
; CHECK: renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
; CHECK: renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14 /* CC::al */, $noreg, $noreg
; CHECK: renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14 /* CC::al */, $noreg
; CHECK: renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14 /* CC::al */, $noreg, $noreg
; CHECK: bb.5.for.cond4.preheader.us:
; CHECK: successors: %bb.6(0x80000000)
; CHECK: liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (load (s32) from %ir.arrayidx12.us)
; CHECK: $q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
; CHECK: $r2 = tMOVr killed $lr, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14 /* CC::al */, $noreg
; CHECK: $r6 = tMOVr $r5, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr $r8, 14 /* CC::al */, $noreg
; CHECK: dead $lr = tMOVr $r0, 14 /* CC::al */, $noreg
; CHECK: $lr = t2DLS renamable $r0
; CHECK: bb.6.vector.body:
; CHECK: successors: %bb.6(0x7c000000), %bb.7(0x04000000)
; CHECK: liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
; CHECK: $q2 = MVE_VORR killed $q1, killed $q1, 0, $noreg, $noreg, undef $q2
; CHECK: MVE_VPST 4, implicit $vpr
; CHECK: renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
; CHECK: renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
; CHECK: renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
; CHECK: renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.6
; CHECK: bb.7.middle.block:
; CHECK: successors: %bb.8(0x04000000), %bb.5(0x7c000000)
; CHECK: liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
; CHECK: renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
; CHECK: renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14 /* CC::al */, $noreg
; CHECK: renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
; CHECK: $lr = tMOVr $r10, 14 /* CC::al */, $noreg
; CHECK: renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
; CHECK: t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14 /* CC::al */, $noreg :: (store (s32) into %ir.27)
; CHECK: renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14 /* CC::al */, $noreg
; CHECK: tCMPhir renamable $r7, $r10, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.5, 1 /* CC::ne */, killed $cpsr
; CHECK: bb.8.for.end16:
; CHECK: successors: %bb.9(0x50000000), %bb.13(0x30000000)
; CHECK: liveins: $lr, $r4, $r12
; CHECK: t2CMPri renamable $lr, 1, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: tBcc %bb.13, 11 /* CC::lt */, killed $cpsr
; CHECK: bb.9.for.body.i57.preheader:
; CHECK: successors: %bb.10(0x80000000)
; CHECK: liveins: $lr, $r4, $r12
; CHECK: renamable $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r1 = IMPLICIT_DEF
; CHECK: bb.10.for.body.i57:
; CHECK: successors: %bb.10(0x7c000000), %bb.11(0x04000000)
; CHECK: liveins: $lr, $r0, $r1, $r4, $r12
; CHECK: renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14 /* CC::al */, $noreg :: (load (s32) from %ir.lsr.iv1)
; CHECK: renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14 /* CC::al */, $noreg
; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 killed renamable $r2, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
; CHECK: tCMPi8 renamable $r1, 0, 14 /* CC::al */, $noreg, implicit-def $cpsr
; CHECK: renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14 /* CC::al */, $noreg, $noreg
; CHECK: t2IT 12, 8, implicit-def $itstate
; CHECK: $r1 = tMOVi8 $noreg, 0, 12 /* CC::gt */, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
; CHECK: renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14 /* CC::al */, $noreg
; CHECK: $lr = t2LEUpdate killed renamable $lr, %bb.10
; CHECK: bb.11.c.exit59.loopexit:
; CHECK: successors: %bb.14(0x80000000)
; CHECK: liveins: $r0, $r12
; CHECK: renamable $r7 = tSXTH killed renamable $r0, 14 /* CC::al */, $noreg
; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
; CHECK: bb.12.c.exit.thread:
; CHECK: successors: %bb.14(0x80000000)
; CHECK: $r0, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: tBL 14 /* CC::al */, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
; CHECK: $r12 = tMOVr killed $r0, 14 /* CC::al */, $noreg
; CHECK: tB %bb.14, 14 /* CC::al */, $noreg
; CHECK: bb.13:
; CHECK: successors: %bb.14(0x80000000)
; CHECK: liveins: $r12
; CHECK: renamable $r7, dead $cpsr = tMOVi8 0, 14 /* CC::al */, $noreg
; CHECK: bb.14.c.exit59:
; CHECK: liveins: $r7, $r12
; CHECK: $r0 = tMOVr killed $r7, 14 /* CC::al */, $noreg
; CHECK: $r1 = tMOVr killed $r12, 14 /* CC::al */, $noreg
; CHECK: $sp = t2LDMIA_UPD $sp, 14 /* CC::al */, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr
; CHECK: tTAILJMPdND @crc16, 14 /* CC::al */, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1
bb.0.entry:
successors: %bb.1(0x50000000), %bb.12(0x30000000)
liveins: $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $lr
$sp = frame-setup t2STMDB_UPD $sp, 14, $noreg, killed $r4, killed $r5, killed $r6, killed $r7, killed $r8, killed $r9, killed $r10, killed $lr
frame-setup CFI_INSTRUCTION def_cfa_offset 32
frame-setup CFI_INSTRUCTION offset $lr, -4
frame-setup CFI_INSTRUCTION offset $r10, -8
frame-setup CFI_INSTRUCTION offset $r9, -12
frame-setup CFI_INSTRUCTION offset $r8, -16
frame-setup CFI_INSTRUCTION offset $r7, -20
frame-setup CFI_INSTRUCTION offset $r6, -24
frame-setup CFI_INSTRUCTION offset $r5, -28
frame-setup CFI_INSTRUCTION offset $r4, -32
tCMPi8 renamable $r0, 1, 14, $noreg, implicit-def $cpsr
t2Bcc %bb.12, 11, killed $cpsr
bb.1.for.body.i.preheader:
successors: %bb.2(0x80000000)
liveins: $r0, $r1, $r2, $r3
$r5 = tMOVr killed $r2, 14, $noreg
$r8 = tMOVr killed $r3, 14, $noreg
$r4 = tMOVr $r1, 14, $noreg
renamable $r6, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r2 = IMPLICIT_DEF
$r10 = tMOVr $r0, 14, $noreg
$lr = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart killed renamable $r0
bb.2.for.body.i:
successors: %bb.2(0x7c000000), %bb.3(0x04000000)
liveins: $lr, $r1, $r2, $r4, $r5, $r6, $r8, $r10
renamable $r3, renamable $r1 = t2LDR_POST killed renamable $r1, 4, 14, $noreg :: (load (s32) from %ir.lsr.iv15)
renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r2 = nsw tADDhirr killed renamable $r2, renamable $r3, 14, $noreg
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
renamable $r7 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
tCMPi8 killed renamable $r3, 0, 14, $noreg, implicit-def $cpsr
renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
tCMPi8 renamable $r2, 0, 14, $noreg, implicit-def $cpsr
renamable $r3 = t2ANDrr killed renamable $r3, killed renamable $r7, 14, $noreg, $noreg
t2IT 12, 8, implicit-def $itstate
$r2 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r2, implicit killed $itstate
renamable $r6 = tADDhirr killed renamable $r6, killed renamable $r3, 14, $noreg
t2LoopEnd renamable $lr, %bb.2, implicit-def dead $cpsr
tB %bb.3, 14, $noreg
bb.3.c.exit:
successors: %bb.4(0x50000000), %bb.14(0x30000000)
liveins: $r4, $r5, $r6, $r8, $r10
renamable $r0 = tSXTH killed renamable $r6, 14, $noreg
tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
$r12 = tMOVr killed $r0, 14, $noreg
renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg
t2CMPri $r10, 1, 14, $noreg, implicit-def $cpsr
tBcc %bb.14, 11, killed $cpsr
bb.4.for.cond4.preheader.us.preheader:
successors: %bb.5(0x80000000)
liveins: $r4, $r5, $r7, $r8, $r10, $r12
renamable $r0 = t2ADDri $r10, 3, 14, $noreg, $noreg
$lr = tMOVr $r10, 14, $noreg
renamable $r0 = t2BICri killed renamable $r0, 3, 14, $noreg, $noreg
renamable $r3 = t2LSLri $r10, 1, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tSUBi3 killed renamable $r0, 4, 14, $noreg
renamable $r0, dead $cpsr = tMOVi8 1, 14, $noreg
renamable $q0 = MVE_VDUP32 renamable $r7, 0, $noreg, $noreg, undef renamable $q0
renamable $r0 = nuw nsw t2ADDrs killed renamable $r0, renamable $r1, 19, 14, $noreg, $noreg
renamable $r1, dead $cpsr = tLSRri killed renamable $r1, 2, 14, $noreg
renamable $r9 = t2SUBrs $r10, killed renamable $r1, 18, 14, $noreg, $noreg
bb.5.for.cond4.preheader.us:
successors: %bb.6(0x80000000)
liveins: $lr, $q0, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
renamable $r1 = t2LDRs renamable $r4, renamable $r7, 2, 14, $noreg :: (load (s32) from %ir.arrayidx12.us)
$q1 = MVE_VORR $q0, $q0, 0, $noreg, $noreg, undef $q1
$r2 = tMOVr killed $lr, 14, $noreg
renamable $q1 = MVE_VMOV_to_lane_32 killed renamable $q1, killed renamable $r1, 0, 14, $noreg
$r6 = tMOVr $r5, 14, $noreg
$r1 = tMOVr $r8, 14, $noreg
$lr = tMOVr $r0, 14, $noreg
$lr = t2DoLoopStart renamable $r0
bb.6.vector.body:
successors: %bb.6(0x7c000000), %bb.7(0x04000000)
liveins: $lr, $q0, $q1, $r0, $r1, $r2, $r3, $r4, $r5, $r6, $r7, $r8, $r9, $r10, $r12
renamable $vpr = MVE_VCTP32 renamable $r2, 0, $noreg, $noreg
$q2 = MVE_VORR killed $q1, $q1, 0, $noreg, $noreg, undef $q2
MVE_VPST 4, implicit $vpr
renamable $r6, renamable $q1 = MVE_VLDRHS32_post killed renamable $r6, 8, 1, renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv1012, align 2)
renamable $r1, renamable $q3 = MVE_VLDRHS32_post killed renamable $r1, 8, 1, killed renamable $vpr, $noreg :: (load (s64) from %ir.lsr.iv46, align 2)
renamable $r2, dead $cpsr = tSUBi8 killed renamable $r2, 4, 14, $noreg
renamable $q1 = nsw MVE_VMULi32 killed renamable $q3, killed renamable $q1, 0, $noreg, $noreg, undef renamable $q1
renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $q1 = MVE_VADDi32 killed renamable $q1, renamable $q2, 0, $noreg, $noreg, undef renamable $q1
t2LoopEnd renamable $lr, %bb.6, implicit-def dead $cpsr
tB %bb.7, 14, $noreg
bb.7.middle.block:
successors: %bb.8(0x04000000), %bb.5(0x7c000000)
liveins: $q0, $q1, $q2, $r0, $r3, $r4, $r5, $r7, $r8, $r9, $r10, $r12
renamable $vpr = MVE_VCTP32 renamable $r9, 0, $noreg, $noreg
renamable $r5 = tADDhirr killed renamable $r5, renamable $r3, 14, $noreg
renamable $q1 = MVE_VPSEL killed renamable $q1, killed renamable $q2, 0, killed renamable $vpr, $noreg
$lr = tMOVr $r10, 14, $noreg
renamable $r2 = MVE_VADDVu32no_acc killed renamable $q1, 0, $noreg, $noreg
t2STRs killed renamable $r2, renamable $r4, renamable $r7, 2, 14, $noreg :: (store (s32) into %ir.27)
renamable $r7, dead $cpsr = nuw nsw tADDi8 killed renamable $r7, 1, 14, $noreg
tCMPhir renamable $r7, $r10, 14, $noreg, implicit-def $cpsr
tBcc %bb.5, 1, killed $cpsr
bb.8.for.end16:
successors: %bb.9(0x50000000), %bb.13(0x30000000)
liveins: $lr, $r4, $r12
t2CMPri renamable $lr, 1, 14, $noreg, implicit-def $cpsr
tBcc %bb.13, 11, killed $cpsr
bb.9.for.body.i57.preheader:
successors: %bb.10(0x80000000)
liveins: $lr, $r4, $r12
renamable $r0, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r1 = IMPLICIT_DEF
$lr = t2DoLoopStart renamable $lr
bb.10.for.body.i57:
successors: %bb.10(0x7c000000), %bb.11(0x04000000)
liveins: $lr, $r0, $r1, $r4, $r12
renamable $r2, renamable $r4 = t2LDR_POST killed renamable $r4, 4, 14, $noreg :: (load (s32) from %ir.lsr.iv1)
renamable $lr = t2LoopDec killed renamable $lr, 1
renamable $r1 = nsw tADDhirr killed renamable $r1, renamable $r2, 14, $noreg
tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr
renamable $r3 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
tCMPi8 killed renamable $r2, 0, 14, $noreg, implicit-def $cpsr
renamable $r2 = t2CSINC $zr, $zr, 13, implicit killed $cpsr
tCMPi8 renamable $r1, 0, 14, $noreg, implicit-def $cpsr
renamable $r2 = t2ANDrr killed renamable $r2, killed renamable $r3, 14, $noreg, $noreg
t2IT 12, 8, implicit-def $itstate
$r1 = tMOVi8 $noreg, 0, 12, killed $cpsr, implicit killed renamable $r1, implicit killed $itstate
renamable $r0 = tADDhirr killed renamable $r0, killed renamable $r2, 14, $noreg
t2LoopEnd renamable $lr, %bb.10, implicit-def dead $cpsr
tB %bb.11, 14, $noreg
bb.11.c.exit59.loopexit:
successors: %bb.14(0x80000000)
liveins: $r0, $r12
renamable $r7 = tSXTH killed renamable $r0, 14, $noreg
tB %bb.14, 14, $noreg
bb.12.c.exit.thread:
successors: %bb.14(0x80000000)
$r0, dead $cpsr = tMOVi8 0, 14, $noreg
renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg
tBL 14, $noreg, @crc16, csr_aapcs, implicit-def dead $lr, implicit $sp, implicit killed $r0, implicit-def $sp, implicit-def $r0
$r12 = tMOVr killed $r0, 14, $noreg
tB %bb.14, 14, $noreg
bb.13:
successors: %bb.14(0x80000000)
liveins: $r12
renamable $r7, dead $cpsr = tMOVi8 0, 14, $noreg
bb.14.c.exit59:
liveins: $r7, $r12
$r0 = tMOVr killed $r7, 14, $noreg
$r1 = tMOVr killed $r12, 14, $noreg
$sp = t2LDMIA_UPD $sp, 14, $noreg, def $r4, def $r5, def $r6, def $r7, def $r8, def $r9, def $r10, def $lr
tTAILJMPdND @crc16, 14, $noreg, implicit $sp, implicit $sp, implicit killed $r0, implicit killed $r1
...
Reference in New Issue View Git Blame Copy Permalink