f988f68064
In ValueTracking.cpp we use a function called computeKnownBitsFromOperator to determine the known bits of a value. For the vscale intrinsic if the function contains the vscale_range attribute we can use the maximum and minimum values of vscale to determine some known zero and one bits. This should help to improve code quality by allowing certain optimisations to take place. Tests added here: Transforms/InstCombine/icmp-vscale.ll Differential Revision: https://reviews.llvm.org/D109883
187 lines
10 KiB
LLVM
187 lines
10 KiB
LLVM
; RUN: opt -mtriple aarch64-linux-gnu -mattr=+sve -loop-vectorize -scalable-vectorization=on -dce -instcombine -S < %s | FileCheck %s
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; Ensure that we can vectorize loops such as:
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; int *ptr = c;
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; for (long long i = 0; i < n; i++) {
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; int X1 = *ptr++;
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; int X2 = *ptr++;
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; a[i] = X1 + 1;
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; b[i] = X2 + 1;
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; }
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; with scalable vectors, including unrolling. The test below makes sure
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; that we can use gather instructions with the correct offsets, taking
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; vscale into account.
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define void @widen_ptr_phi_unrolled(i32* noalias nocapture %a, i32* noalias nocapture %b, i32* nocapture readonly %c, i64 %n) #0 {
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; CHECK-LABEL: @widen_ptr_phi_unrolled(
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; CHECK: vector.body:
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; CHECK-NEXT: [[POINTER_PHI:%.*]] = phi i32* [ %c, %vector.ph ], [ %[[PTR_IND:.*]], %vector.body ]
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; CHECK: [[TMP5:%.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: [[TMP6:%.*]] = shl nuw nsw i64 [[TMP5]], 2
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; CHECK-NEXT: [[TMP7:%.*]] = shl nuw nsw i64 [[TMP5]], 4
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; CHECK-NEXT: [[TMP8:%.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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; CHECK-NEXT: [[VECTOR_GEP:%.*]] = shl <vscale x 4 x i64> [[TMP8]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: [[TMP9:%.*]] = getelementptr i32, i32* [[POINTER_PHI]], <vscale x 4 x i64> [[VECTOR_GEP]]
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; CHECK-NEXT: [[DOTSPLATINSERT2:%.*]] = insertelement <vscale x 4 x i64> poison, i64 [[TMP6]], i32 0
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; CHECK-NEXT: [[DOTSPLAT3:%.*]] = shufflevector <vscale x 4 x i64> [[DOTSPLATINSERT2]], <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP10:%.*]] = call <vscale x 4 x i64> @llvm.experimental.stepvector.nxv4i64()
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; CHECK-NEXT: [[TMP11:%.*]] = add <vscale x 4 x i64> [[DOTSPLAT3]], [[TMP10]]
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; CHECK-NEXT: [[VECTOR_GEP4:%.*]] = shl <vscale x 4 x i64> [[TMP11]], shufflevector (<vscale x 4 x i64> insertelement (<vscale x 4 x i64> poison, i64 1, i32 0), <vscale x 4 x i64> poison, <vscale x 4 x i32> zeroinitializer)
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; CHECK-NEXT: [[TMP12:%.*]] = getelementptr i32, i32* [[POINTER_PHI]], <vscale x 4 x i64> [[VECTOR_GEP4]]
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; CHECK-NEXT: [[TMP13:%.*]] = getelementptr inbounds i32, <vscale x 4 x i32*> [[TMP9]], i64 1
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; CHECK-NEXT: [[TMP14:%.*]] = getelementptr inbounds i32, <vscale x 4 x i32*> [[TMP12]], i64 1
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; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP9]],
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; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP12]],
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; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP13]],
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; CHECK-NEXT: {{%.*}} = call <vscale x 4 x i32> @llvm.masked.gather.nxv4i32.nxv4p0i32(<vscale x 4 x i32*> [[TMP14]],
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; CHECK: [[PTR_IND]] = getelementptr i32, i32* [[POINTER_PHI]], i64 [[TMP7]]
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%ptr.014 = phi i32* [ %incdec.ptr1, %for.body ], [ %c, %entry ]
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%i.013 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%incdec.ptr = getelementptr inbounds i32, i32* %ptr.014, i64 1
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%0 = load i32, i32* %ptr.014, align 4
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%incdec.ptr1 = getelementptr inbounds i32, i32* %ptr.014, i64 2
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%1 = load i32, i32* %incdec.ptr, align 4
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%add = add nsw i32 %0, 1
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%arrayidx = getelementptr inbounds i32, i32* %a, i64 %i.013
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store i32 %add, i32* %arrayidx, align 4
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%add2 = add nsw i32 %1, 1
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%arrayidx3 = getelementptr inbounds i32, i32* %b, i64 %i.013
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store i32 %add2, i32* %arrayidx3, align 4
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%inc = add nuw nsw i64 %i.013, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %for.exit, label %for.body, !llvm.loop !0
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for.exit: ; preds = %for.body
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ret void
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}
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; Ensure we can vectorise loops without interleaving, e.g.:
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; int *D = dst;
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; int *S = src;
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; for (long long i = 0; i < n; i++) {
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; *D = *S * 2;
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; D++;
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; S++;
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; }
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; This takes us down a different codepath to the test above, where
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; here we treat the PHIs as being uniform.
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define void @widen_2ptrs_phi_unrolled(i32* noalias nocapture %dst, i32* noalias nocapture readonly %src, i64 %n) #0 {
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; CHECK-LABEL: @widen_2ptrs_phi_unrolled(
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; CHECK: vector.body:
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; CHECK-NEXT: %[[IDX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK-NEXT: %[[LGEP1:.*]] = getelementptr i32, i32* %src, i64 %[[IDX]]
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; CHECK-NEXT: %[[SGEP1:.*]] = getelementptr i32, i32* %dst, i64 %[[IDX]]
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; CHECK-NEXT: %[[LPTR1:.*]] = bitcast i32* %[[LGEP1]] to <vscale x 4 x i32>*
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; CHECK-NEXT: %{{.*}} = load <vscale x 4 x i32>, <vscale x 4 x i32>* %[[LPTR1]], align 4
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; CHECK-NEXT: %[[VSCALE1:.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: %[[TMP1:.*]] = shl nuw nsw i32 %[[VSCALE1]], 2
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; CHECK-NEXT: %[[TMP2:.*]] = zext i32 %[[TMP1]] to i64
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; CHECK-NEXT: %[[LGEP2:.*]] = getelementptr i32, i32* %[[LGEP1]], i64 %[[TMP2]]
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; CHECK-NEXT: %[[LPTR2:.*]] = bitcast i32* %[[LGEP2]] to <vscale x 4 x i32>*
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; CHECK-NEXT: %{{.*}} = load <vscale x 4 x i32>, <vscale x 4 x i32>* %[[LPTR2]], align 4
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; CHECK: %[[SPTR1:.*]] = bitcast i32* %[[SGEP1]] to <vscale x 4 x i32>*
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; CHECK-NEXT: store <vscale x 4 x i32> %{{.*}}, <vscale x 4 x i32>* %[[SPTR1]], align 4
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; CHECK-NEXT: %[[VSCALE2:.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: %[[TMP3:.*]] = shl nuw nsw i32 %[[VSCALE2]], 2
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; CHECK-NEXT: %[[TMP4:.*]] = zext i32 %[[TMP3]] to i64
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; CHECK-NEXT: %[[SGEP2:.*]] = getelementptr i32, i32* %[[SGEP1]], i64 %[[TMP4]]
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; CHECK-NEXT: %[[SPTR2:.*]] = bitcast i32* %[[SGEP2]] to <vscale x 4 x i32>*
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; CHECK-NEXT: store <vscale x 4 x i32> %{{.*}}, <vscale x 4 x i32>* %[[SPTR2]], align 4
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entry:
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br label %for.body
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for.body: ; preds = %entry, %for.body
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%i.011 = phi i64 [ %inc, %for.body ], [ 0, %entry ]
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%S.010 = phi i32* [ %incdec.ptr1, %for.body ], [ %src, %entry ]
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%D.09 = phi i32* [ %incdec.ptr, %for.body ], [ %dst, %entry ]
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%0 = load i32, i32* %S.010, align 4
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%mul = shl nsw i32 %0, 1
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store i32 %mul, i32* %D.09, align 4
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%incdec.ptr = getelementptr inbounds i32, i32* %D.09, i64 1
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%incdec.ptr1 = getelementptr inbounds i32, i32* %S.010, i64 1
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%inc = add nuw nsw i64 %i.011, 1
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%exitcond.not = icmp eq i64 %inc, %n
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br i1 %exitcond.not, label %for.cond.cleanup, label %for.body, !llvm.loop !0
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for.cond.cleanup: ; preds = %for.body
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ret void
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}
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;
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; Check multiple pointer induction variables where only one is recognized as
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; uniform and remains uniform after vectorization. The other pointer induction
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; variable is not recognized as uniform and is not uniform after vectorization
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; because it is stored to memory.
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;
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define i32 @pointer_iv_mixed(i32* noalias %a, i32** noalias %b, i64 %n) #0 {
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; CHECK-LABEL: @pointer_iv_mixed(
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; CHECK: vector.body
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; CHECK: %[[IDX:.*]] = phi i64 [ 0, %vector.ph ], [ %{{.*}}, %vector.body ]
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; CHECK: %[[STEPVEC:.*]] = call <vscale x 2 x i64> @llvm.experimental.stepvector.nxv2i64()
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; CHECK-NEXT: %[[TMP1:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[IDX]], i32 0
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; CHECK-NEXT: %[[TMP2:.*]] = shufflevector <vscale x 2 x i64> %[[TMP1]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[VECIND1:.*]] = add <vscale x 2 x i64> %[[TMP2]], %[[STEPVEC]]
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; CHECK-NEXT: %[[APTRS1:.*]] = getelementptr i32, i32* %a, <vscale x 2 x i64> %[[VECIND1]]
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; CHECK-NEXT: %[[GEPA1:.*]] = getelementptr i32, i32* %a, i64 %[[IDX]]
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; CHECK-NEXT: %[[VSCALE64:.*]] = call i64 @llvm.vscale.i64()
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; CHECK-NEXT: %[[VSCALE64X2:.*]] = shl nuw nsw i64 %[[VSCALE64]], 1
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; CHECK-NEXT: %[[TMP3:.*]] = insertelement <vscale x 2 x i64> poison, i64 %[[VSCALE64X2]], i32 0
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; CHECK-NEXT: %[[TMP4:.*]] = shufflevector <vscale x 2 x i64> %[[TMP3]], <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer
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; CHECK-NEXT: %[[TMP5:.*]] = add <vscale x 2 x i64> %[[TMP4]], %[[STEPVEC]]
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; CHECK-NEXT: %[[VECIND2:.*]] = add <vscale x 2 x i64> %[[TMP2]], %[[TMP5]]
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; CHECK-NEXT: %[[APTRS2:.*]] = getelementptr i32, i32* %a, <vscale x 2 x i64> %[[VECIND2]]
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; CHECK-NEXT: %[[GEPB1:.*]] = getelementptr i32*, i32** %b, i64 %[[IDX]]
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; The following checks that there is no extractelement after
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; vectorization when the stepvector has multiple uses, which demonstrates
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; the removal of a redundant fmov instruction in the generated asm code.
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; CHECK-NOT: %[[EXTRACT:.*]] = extractelement <vscale x 2 x i32*> [[APTRS1]], i32 0
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; CHECK: %[[BPTR1:.*]] = bitcast i32** %[[GEPB1]] to <vscale x 2 x i32*>*
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; CHECK-NEXT: store <vscale x 2 x i32*> %[[APTRS1]], <vscale x 2 x i32*>* %[[BPTR1]], align 8
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; CHECK: %[[VSCALE32:.*]] = call i32 @llvm.vscale.i32()
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; CHECK-NEXT: %[[VSCALE32X2:.*]] = shl nuw nsw i32 %[[VSCALE32]], 1
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; CHECK-NEXT: %[[TMP6:.*]] = zext i32 %[[VSCALE32X2]] to i64
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; CHECK-NEXT: %[[GEPB2:.*]] = getelementptr i32*, i32** %[[GEPB1]], i64 %[[TMP6]]
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; CHECK-NEXT: %[[BPTR2:.*]] = bitcast i32** %[[GEPB2]] to <vscale x 2 x i32*>*
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; CHECK-NEXT store <vscale x 2 x i32*> %[[APTRS2]], <vscale x 2 x i32*>* %[[BPTR2]], align 8
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entry:
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br label %for.body
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for.body:
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%i = phi i64 [ %i.next, %for.body ], [ 0, %entry ]
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%p = phi i32* [ %tmp3, %for.body ], [ %a, %entry ]
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%q = phi i32** [ %tmp4, %for.body ], [ %b, %entry ]
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%tmp0 = phi i32 [ %tmp2, %for.body ], [ 0, %entry ]
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%tmp1 = load i32, i32* %p, align 8
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%tmp2 = add i32 %tmp1, %tmp0
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store i32* %p, i32** %q, align 8
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%tmp3 = getelementptr inbounds i32, i32* %p, i32 1
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%tmp4 = getelementptr inbounds i32*, i32** %q, i32 1
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%i.next = add nuw nsw i64 %i, 1
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%cond = icmp slt i64 %i.next, %n
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br i1 %cond, label %for.body, label %for.end, !llvm.loop !6
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for.end:
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%tmp5 = phi i32 [ %tmp2, %for.body ]
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ret i32 %tmp5
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}
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attributes #0 = { vscale_range(0, 16) }
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!0 = distinct !{!0, !1, !2, !3, !4, !5}
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!1 = !{!"llvm.loop.mustprogress"}
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!2 = !{!"llvm.loop.vectorize.width", i32 4}
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!3 = !{!"llvm.loop.vectorize.scalable.enable", i1 true}
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!4 = !{!"llvm.loop.vectorize.enable", i1 true}
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!5 = !{!"llvm.loop.interleave.count", i32 2}
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!6 = distinct !{!6, !1, !7, !3, !4, !5}
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!7 = !{!"llvm.loop.vectorize.width", i32 2}
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