Files
clang-p2996/llvm/lib/CodeGen/SelectionDAG/LegalizeVectorOps.cpp
Benjamin Kramer 5ea0349ef5 When lowering an inreg sext first shift left, then right arithmetically.
Shifting right two times will only yield zero. Should fix
SingleSource/UnitTests/SignlessTypes/factor.

llvm-svn: 172322
2013-01-12 19:06:44 +00:00

24 KiB