Sasa Stankovic b976fee83c [mips] Expand BuildPairF64 to a spill and reload when the O32 FPXX ABI is ...

enabled and mthc1 and dmtc1 are not available (e.g. on MIPS32r1)

This prevents the upper 32-bits of a double precision value from being moved to
the FPU with mtc1 to an odd-numbered FPU register. This is necessary to ensure
that the code generated executes correctly regardless of the current FPU mode.

MIPS32r2 and above continues to use mtc1/mthc1, while MIPS-IV and above continue
to use dmtc1.

Differential Revision: http://reviews.llvm.org/D4465

llvm-svn: 212930

2014-07-14 09:40:29 +00:00

4.0 KiB

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