bef3eb8344
Adds NVPTX intrinsics and builtins for CUDA PTX cvt instructions for sm80 architectures and above. Requires ptx 7.0. PTX ISA description of cvt instructions : https://docs.nvidia.com/cuda/parallel-thread-execution/index.html#data-movement-and-conversion-instructions-cvt Signed-off-by: JackAKirk <jack.kirk@codeplay.com> Differential Revision: https://reviews.llvm.org/D116673
318 lines
8.6 KiB
C++
318 lines
8.6 KiB
C++
//===-- NVPTXInstPrinter.cpp - PTX assembly instruction printing ----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// Print MCInst instructions to .ptx format.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/NVPTXInstPrinter.h"
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#include "MCTargetDesc/NVPTXBaseInfo.h"
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#include "NVPTX.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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#include <cctype>
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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#include "NVPTXGenAsmWriter.inc"
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NVPTXInstPrinter::NVPTXInstPrinter(const MCAsmInfo &MAI, const MCInstrInfo &MII,
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const MCRegisterInfo &MRI)
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: MCInstPrinter(MAI, MII, MRI) {}
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void NVPTXInstPrinter::printRegName(raw_ostream &OS, unsigned RegNo) const {
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// Decode the virtual register
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// Must be kept in sync with NVPTXAsmPrinter::encodeVirtualRegister
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unsigned RCId = (RegNo >> 28);
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switch (RCId) {
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default: report_fatal_error("Bad virtual register encoding");
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case 0:
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// This is actually a physical register, so defer to the autogenerated
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// register printer
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OS << getRegisterName(RegNo);
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return;
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case 1:
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OS << "%p";
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break;
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case 2:
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OS << "%rs";
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break;
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case 3:
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OS << "%r";
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break;
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case 4:
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OS << "%rd";
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break;
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case 5:
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OS << "%f";
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break;
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case 6:
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OS << "%fd";
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break;
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case 7:
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OS << "%h";
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break;
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case 8:
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OS << "%hh";
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break;
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}
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unsigned VReg = RegNo & 0x0FFFFFFF;
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OS << VReg;
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}
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void NVPTXInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &OS) {
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printInstruction(MI, Address, OS);
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// Next always print the annotation.
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printAnnotation(OS, Annot);
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}
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void NVPTXInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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unsigned Reg = Op.getReg();
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printRegName(O, Reg);
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} else if (Op.isImm()) {
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O << markup("<imm:") << formatImm(Op.getImm()) << markup(">");
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} else {
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assert(Op.isExpr() && "Unknown operand kind in printOperand");
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Op.getExpr()->print(O, &MAI);
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}
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}
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void NVPTXInstPrinter::printCvtMode(const MCInst *MI, int OpNum, raw_ostream &O,
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const char *Modifier) {
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const MCOperand &MO = MI->getOperand(OpNum);
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int64_t Imm = MO.getImm();
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if (strcmp(Modifier, "ftz") == 0) {
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// FTZ flag
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if (Imm & NVPTX::PTXCvtMode::FTZ_FLAG)
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O << ".ftz";
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} else if (strcmp(Modifier, "sat") == 0) {
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// SAT flag
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if (Imm & NVPTX::PTXCvtMode::SAT_FLAG)
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O << ".sat";
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} else if (strcmp(Modifier, "relu") == 0) {
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// RELU flag
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if (Imm & NVPTX::PTXCvtMode::RELU_FLAG)
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O << ".relu";
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} else if (strcmp(Modifier, "base") == 0) {
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// Default operand
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switch (Imm & NVPTX::PTXCvtMode::BASE_MASK) {
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default:
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return;
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case NVPTX::PTXCvtMode::NONE:
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break;
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case NVPTX::PTXCvtMode::RNI:
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O << ".rni";
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break;
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case NVPTX::PTXCvtMode::RZI:
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O << ".rzi";
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break;
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case NVPTX::PTXCvtMode::RMI:
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O << ".rmi";
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break;
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case NVPTX::PTXCvtMode::RPI:
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O << ".rpi";
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break;
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case NVPTX::PTXCvtMode::RN:
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O << ".rn";
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break;
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case NVPTX::PTXCvtMode::RZ:
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O << ".rz";
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break;
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case NVPTX::PTXCvtMode::RM:
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O << ".rm";
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break;
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case NVPTX::PTXCvtMode::RP:
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O << ".rp";
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break;
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case NVPTX::PTXCvtMode::RNA:
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O << ".rna";
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break;
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}
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} else {
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llvm_unreachable("Invalid conversion modifier");
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}
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}
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void NVPTXInstPrinter::printCmpMode(const MCInst *MI, int OpNum, raw_ostream &O,
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const char *Modifier) {
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const MCOperand &MO = MI->getOperand(OpNum);
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int64_t Imm = MO.getImm();
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if (strcmp(Modifier, "ftz") == 0) {
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// FTZ flag
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if (Imm & NVPTX::PTXCmpMode::FTZ_FLAG)
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O << ".ftz";
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} else if (strcmp(Modifier, "base") == 0) {
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switch (Imm & NVPTX::PTXCmpMode::BASE_MASK) {
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default:
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return;
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case NVPTX::PTXCmpMode::EQ:
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O << ".eq";
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break;
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case NVPTX::PTXCmpMode::NE:
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O << ".ne";
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break;
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case NVPTX::PTXCmpMode::LT:
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O << ".lt";
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break;
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case NVPTX::PTXCmpMode::LE:
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O << ".le";
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break;
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case NVPTX::PTXCmpMode::GT:
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O << ".gt";
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break;
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case NVPTX::PTXCmpMode::GE:
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O << ".ge";
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break;
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case NVPTX::PTXCmpMode::LO:
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O << ".lo";
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break;
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case NVPTX::PTXCmpMode::LS:
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O << ".ls";
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break;
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case NVPTX::PTXCmpMode::HI:
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O << ".hi";
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break;
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case NVPTX::PTXCmpMode::HS:
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O << ".hs";
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break;
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case NVPTX::PTXCmpMode::EQU:
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O << ".equ";
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break;
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case NVPTX::PTXCmpMode::NEU:
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O << ".neu";
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break;
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case NVPTX::PTXCmpMode::LTU:
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O << ".ltu";
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break;
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case NVPTX::PTXCmpMode::LEU:
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O << ".leu";
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break;
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case NVPTX::PTXCmpMode::GTU:
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O << ".gtu";
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break;
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case NVPTX::PTXCmpMode::GEU:
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O << ".geu";
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break;
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case NVPTX::PTXCmpMode::NUM:
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O << ".num";
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break;
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case NVPTX::PTXCmpMode::NotANumber:
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O << ".nan";
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break;
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}
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} else {
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llvm_unreachable("Empty Modifier");
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}
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}
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void NVPTXInstPrinter::printLdStCode(const MCInst *MI, int OpNum,
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raw_ostream &O, const char *Modifier) {
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if (Modifier) {
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const MCOperand &MO = MI->getOperand(OpNum);
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int Imm = (int) MO.getImm();
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if (!strcmp(Modifier, "volatile")) {
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if (Imm)
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O << ".volatile";
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} else if (!strcmp(Modifier, "addsp")) {
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switch (Imm) {
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case NVPTX::PTXLdStInstCode::GLOBAL:
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O << ".global";
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break;
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case NVPTX::PTXLdStInstCode::SHARED:
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O << ".shared";
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break;
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case NVPTX::PTXLdStInstCode::LOCAL:
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O << ".local";
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break;
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case NVPTX::PTXLdStInstCode::PARAM:
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O << ".param";
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break;
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case NVPTX::PTXLdStInstCode::CONSTANT:
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O << ".const";
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break;
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case NVPTX::PTXLdStInstCode::GENERIC:
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break;
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default:
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llvm_unreachable("Wrong Address Space");
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}
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} else if (!strcmp(Modifier, "sign")) {
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if (Imm == NVPTX::PTXLdStInstCode::Signed)
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O << "s";
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else if (Imm == NVPTX::PTXLdStInstCode::Unsigned)
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O << "u";
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else if (Imm == NVPTX::PTXLdStInstCode::Untyped)
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O << "b";
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else if (Imm == NVPTX::PTXLdStInstCode::Float)
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O << "f";
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else
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llvm_unreachable("Unknown register type");
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} else if (!strcmp(Modifier, "vec")) {
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if (Imm == NVPTX::PTXLdStInstCode::V2)
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O << ".v2";
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else if (Imm == NVPTX::PTXLdStInstCode::V4)
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O << ".v4";
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} else
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llvm_unreachable("Unknown Modifier");
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} else
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llvm_unreachable("Empty Modifier");
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}
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void NVPTXInstPrinter::printMmaCode(const MCInst *MI, int OpNum, raw_ostream &O,
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const char *Modifier) {
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const MCOperand &MO = MI->getOperand(OpNum);
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int Imm = (int)MO.getImm();
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if (Modifier == nullptr || strcmp(Modifier, "version") == 0) {
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O << Imm; // Just print out PTX version
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} else if (strcmp(Modifier, "aligned") == 0) {
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// PTX63 requires '.aligned' in the name of the instruction.
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if (Imm >= 63)
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O << ".aligned";
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} else
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llvm_unreachable("Unknown Modifier");
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}
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void NVPTXInstPrinter::printMemOperand(const MCInst *MI, int OpNum,
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raw_ostream &O, const char *Modifier) {
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printOperand(MI, OpNum, O);
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if (Modifier && !strcmp(Modifier, "add")) {
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O << ", ";
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printOperand(MI, OpNum + 1, O);
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} else {
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if (MI->getOperand(OpNum + 1).isImm() &&
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MI->getOperand(OpNum + 1).getImm() == 0)
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return; // don't print ',0' or '+0'
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O << "+";
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printOperand(MI, OpNum + 1, O);
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}
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}
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void NVPTXInstPrinter::printProtoIdent(const MCInst *MI, int OpNum,
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raw_ostream &O, const char *Modifier) {
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const MCOperand &Op = MI->getOperand(OpNum);
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assert(Op.isExpr() && "Call prototype is not an MCExpr?");
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const MCExpr *Expr = Op.getExpr();
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const MCSymbol &Sym = cast<MCSymbolRefExpr>(Expr)->getSymbol();
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O << Sym.getName();
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}
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