Files
clang-p2996/llvm/lib/Target/RISCV/RISCVSExtWRemoval.cpp
Mohammed Nurul Hoque 7afa44f5f5 [RISCV] Add more sign-extending ops to MIR sext.w pass.
This patch adds single-bit and bit-counting ops to list of sign-extending ops.

A single-bit write propagates sign-extendedness if it's not in the sign-bits.

Bit extraction and bit counting always outputs a small number, so sign-extended.

Reviewed By: craig.topper

Differential Revision: https://reviews.llvm.org/D121152
2022-03-18 18:21:17 +08:00

8.4 KiB