5aa56b2429
This isn't a real with the codegen, it's a previously known bug in clang which
causes non-deterministic failures due to garbage bits in undef registers being
used in saturating instructions.
I'm disabling the result checking for the test until this issue is resolved.
This reverts commit 6c8168324b.
218 lines
6.8 KiB
YAML
218 lines
6.8 KiB
YAML
# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
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# RUN: llc -verify-machineinstrs -mtriple aarch64-unknown-unknown -run-pass=instruction-select %s -o - | FileCheck %s
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---
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name: v8s16_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q1, $w0
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; CHECK-LABEL: name: v8s16_gpr
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; CHECK: liveins: $q1, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[INSvi16gpr:%[0-9]+]]:fpr128 = INSvi16gpr [[COPY1]], 1, [[COPY]]
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; CHECK: $q0 = COPY [[INSvi16gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(s32) = COPY $w0
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%trunc:gpr(s16) = G_TRUNC %0
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%1:fpr(<8 x s16>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %trunc:gpr(s16), %3:gpr(s32)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v8s16_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q1, $h0
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; CHECK-LABEL: name: v8s16_fpr
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; CHECK: liveins: $q1, $h0
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; CHECK: [[COPY:%[0-9]+]]:fpr16 = COPY $h0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.hsub
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; CHECK: [[INSvi16lane:%[0-9]+]]:fpr128 = INSvi16lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi16lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s16) = COPY $h0
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%1:fpr(<8 x s16>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<8 x s16>) = G_INSERT_VECTOR_ELT %1, %0(s16), %3(s32)
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$q0 = COPY %2(<8 x s16>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v4s32_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q1, $s0
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; CHECK-LABEL: name: v4s32_fpr
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; CHECK: liveins: $q1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.ssub
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; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi32lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s32) = COPY $s0
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%1:fpr(<4 x s32>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v4s32_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $w0
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; CHECK-LABEL: name: v4s32_gpr
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; CHECK: liveins: $q0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[COPY1]], 1, [[COPY]]
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; CHECK: $q0 = COPY [[INSvi32gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(s32) = COPY $w0
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%1:fpr(<4 x s32>) = COPY $q0
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<4 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$q0 = COPY %2(<4 x s32>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s64_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $q1
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; CHECK-LABEL: name: v2s64_fpr
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; CHECK: liveins: $d0, $q1
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; CHECK: [[COPY:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY]], %subreg.dsub
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; CHECK: [[INSvi64lane:%[0-9]+]]:fpr128 = INSvi64lane [[COPY1]], 1, [[INSERT_SUBREG]], 0
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; CHECK: $q0 = COPY [[INSvi64lane]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:fpr(s64) = COPY $d0
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%1:fpr(<2 x s64>) = COPY $q1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s64_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $q0, $x0
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; CHECK-LABEL: name: v2s64_gpr
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; CHECK: liveins: $q0, $x0
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; CHECK: [[COPY:%[0-9]+]]:gpr64 = COPY $x0
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; CHECK: [[COPY1:%[0-9]+]]:fpr128 = COPY $q0
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; CHECK: [[INSvi64gpr:%[0-9]+]]:fpr128 = INSvi64gpr [[COPY1]], 0, [[COPY]]
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; CHECK: $q0 = COPY [[INSvi64gpr]]
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; CHECK: RET_ReallyLR implicit $q0
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%0:gpr(s64) = COPY $x0
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%1:fpr(<2 x s64>) = COPY $q0
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%3:gpr(s32) = G_CONSTANT i32 0
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%2:fpr(<2 x s64>) = G_INSERT_VECTOR_ELT %1, %0(s64), %3(s32)
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$q0 = COPY %2(<2 x s64>)
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RET_ReallyLR implicit $q0
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...
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---
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name: v2s32_fpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d1, $s0
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; CHECK-LABEL: name: v2s32_fpr
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; CHECK: liveins: $d1, $s0
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; CHECK: [[COPY:%[0-9]+]]:fpr32 = COPY $s0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d1
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[DEF1:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG1:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF1]], [[COPY]], %subreg.ssub
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; CHECK: [[INSvi32lane:%[0-9]+]]:fpr128 = INSvi32lane [[INSERT_SUBREG]], 1, [[INSERT_SUBREG1]], 0
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32lane]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:fpr(s32) = COPY $s0
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%1:fpr(<2 x s32>) = COPY $d1
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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---
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name: v2s32_gpr
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alignment: 4
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legalized: true
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regBankSelected: true
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tracksRegLiveness: true
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body: |
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bb.0:
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liveins: $d0, $w0
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; CHECK-LABEL: name: v2s32_gpr
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; CHECK: liveins: $d0, $w0
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; CHECK: [[COPY:%[0-9]+]]:gpr32 = COPY $w0
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; CHECK: [[COPY1:%[0-9]+]]:fpr64 = COPY $d0
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; CHECK: [[DEF:%[0-9]+]]:fpr128 = IMPLICIT_DEF
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; CHECK: [[INSERT_SUBREG:%[0-9]+]]:fpr128 = INSERT_SUBREG [[DEF]], [[COPY1]], %subreg.dsub
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; CHECK: [[INSvi32gpr:%[0-9]+]]:fpr128 = INSvi32gpr [[INSERT_SUBREG]], 1, [[COPY]]
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; CHECK: [[COPY2:%[0-9]+]]:fpr64 = COPY [[INSvi32gpr]].dsub
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; CHECK: $d0 = COPY [[COPY2]]
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; CHECK: RET_ReallyLR implicit $d0
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%0:gpr(s32) = COPY $w0
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%1:fpr(<2 x s32>) = COPY $d0
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%3:gpr(s32) = G_CONSTANT i32 1
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%2:fpr(<2 x s32>) = G_INSERT_VECTOR_ELT %1, %0(s32), %3(s32)
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$d0 = COPY %2(<2 x s32>)
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RET_ReallyLR implicit $d0
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...
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