61f69153e8
As of 8dacca943a, we sign extend the atomic loaded
operand for signed subword comparisons. However, the assumption that the other
operand is correctly sign extended doesn't always hold. This patch sign extends
the other operand if it needs to be sign extended.
This is a second fix for https://bugs.llvm.org/show_bug.cgi?id=30451
Differential revision: https://reviews.llvm.org/D94058
106 lines
2.9 KiB
LLVM
106 lines
2.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=powerpc64le-linux-gnu < %s | FileCheck %s
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define i16 @SEXTParam(i16 signext %0) #0 {
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; CHECK-LABEL: SEXTParam:
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; CHECK: # %bb.0: # %top
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: sth 4, -4(1)
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; CHECK-NEXT: addi 4, 1, -4
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: .LBB0_1: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: lharx 5, 0, 4
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; CHECK-NEXT: extsh 5, 5
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; CHECK-NEXT: cmpw 3, 5
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; CHECK-NEXT: bge 0, .LBB0_3
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; CHECK-NEXT: # %bb.2: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: sthcx. 3, 0, 4
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; CHECK-NEXT: bne 0, .LBB0_1
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; CHECK-NEXT: .LBB0_3: # %top
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: lhz 3, -4(1)
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; CHECK-NEXT: cmpd 7, 3, 3
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; CHECK-NEXT: bne- 7, .+4
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; CHECK-NEXT: isync
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; CHECK-NEXT: blr
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top:
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%1 = alloca i16, align 4
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%2 = bitcast i16* %1 to i8*
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store i16 0, i16* %1, align 4
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%rv.i = atomicrmw min i16* %1, i16 %0 acq_rel
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%rv.i2 = load atomic i16, i16* %1 acquire, align 16
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ret i16 %rv.i2
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}
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define i16 @noSEXTParam(i16 %0) #0 {
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; CHECK-LABEL: noSEXTParam:
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; CHECK: # %bb.0: # %top
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: extsh 3, 3
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; CHECK-NEXT: sth 4, -4(1)
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; CHECK-NEXT: addi 4, 1, -4
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: .LBB1_1: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: lharx 5, 0, 4
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; CHECK-NEXT: extsh 5, 5
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; CHECK-NEXT: cmpw 3, 5
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; CHECK-NEXT: bge 0, .LBB1_3
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; CHECK-NEXT: # %bb.2: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: sthcx. 3, 0, 4
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; CHECK-NEXT: bne 0, .LBB1_1
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; CHECK-NEXT: .LBB1_3: # %top
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: lhz 3, -4(1)
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; CHECK-NEXT: cmpd 7, 3, 3
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; CHECK-NEXT: bne- 7, .+4
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; CHECK-NEXT: isync
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; CHECK-NEXT: blr
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top:
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%1 = alloca i16, align 4
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%2 = bitcast i16* %1 to i8*
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store i16 0, i16* %1, align 4
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%rv.i = atomicrmw min i16* %1, i16 %0 acq_rel
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%rv.i2 = load atomic i16, i16* %1 acquire, align 16
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ret i16 %rv.i2
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}
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define i16 @noSEXTLoad(i16 *%p) #0 {
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; CHECK-LABEL: noSEXTLoad:
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; CHECK: # %bb.0: # %top
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; CHECK-NEXT: lhz 5, 0(3)
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; CHECK-NEXT: li 4, 0
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; CHECK-NEXT: addi 3, 1, -4
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; CHECK-NEXT: sth 4, -4(1)
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; CHECK-NEXT: extsh 4, 5
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: .LBB2_1: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: lharx 5, 0, 3
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; CHECK-NEXT: extsh 5, 5
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; CHECK-NEXT: cmpw 4, 5
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; CHECK-NEXT: bge 0, .LBB2_3
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; CHECK-NEXT: # %bb.2: # %top
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; CHECK-NEXT: #
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; CHECK-NEXT: sthcx. 4, 0, 3
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; CHECK-NEXT: bne 0, .LBB2_1
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; CHECK-NEXT: .LBB2_3: # %top
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; CHECK-NEXT: lwsync
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; CHECK-NEXT: lhz 3, -4(1)
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; CHECK-NEXT: cmpd 7, 3, 3
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; CHECK-NEXT: bne- 7, .+4
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; CHECK-NEXT: isync
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; CHECK-NEXT: blr
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top:
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%0 = load i16, i16* %p, align 2
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%1 = alloca i16, align 4
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%2 = bitcast i16* %1 to i8*
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store i16 0, i16* %1, align 4
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%rv.i = atomicrmw min i16* %1, i16 %0 acq_rel
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%rv.i2 = load atomic i16, i16* %1 acquire, align 16
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ret i16 %rv.i2
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}
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attributes #0 = { nounwind }
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