Matthias Braun de5fea2c30 MIRParser: Allow regclass specification on operand ...

You can now define the register class of a virtual register on the
operand itself avoiding the need to use a "registers:" block.

Example: "%0:gr64 = COPY %rax"

Differential Revision: https://reviews.llvm.org/D22398

llvm-svn: 292321

2017-01-18 00:59:19 +00:00

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