caio/clang-p2996
1
0
Fork 0
Code Issues Pull Requests Actions Packages Projects Releases Wiki Activity
Files
c1fa8179d4e5300a67ebdf41916a18f9c6330121
clang-p2996/llvm/lib/Target/RISCV
History
Luke Lau d255e0f997 [RISCV] Peak through BITCAST in isUsedByReturnOnly 
A follow up to 47b1f8362a,
This covers some more cases on soft-float ABIs with the f/d extension.
I left the TODO in as there is still the case where we need to handle rv32i without f/d, but that looks like it requires changes to SelectionDAGLegalize::ExpandFPLibCall

Reviewed By: asb, reames

Differential Revision: https://reviews.llvm.org/D142911
2023-01-30 23:41:14 +00:00
..
AsmParser
[RISCV] Use custom operand parsing for FenceArg.
2023-01-30 12:31:00 -08:00
Disassembler
[RISCV] Implement assembler support for XTHeadVdot
2022-12-26 19:05:22 +08:00
GISel
…
MCA
…
MCTargetDesc
[RISCV] Replace multiple ifs with a switch. NFC
2023-01-30 09:53:48 -08:00
TargetInfo
…
CMakeLists.txt
…
RISCV.h
…
RISCV.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVAsmPrinter.cpp
[RISCV] Use canonical move instruction in RISCVAsmPrinter::EmitHwasanMemaccessSymbols.
2023-01-18 11:38:39 -08:00
RISCVCallingConv.td
…
RISCVCodeGenPrepare.cpp
…
RISCVExpandAtomicPseudoInsts.cpp
…
RISCVExpandPseudoInsts.cpp
…
RISCVFeatures.td
[RISCV] Add MC support of RISCV Zcb Extension
2023-01-26 12:54:00 -08:00
RISCVFrameLowering.cpp
…
RISCVFrameLowering.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVGatherScatterLowering.cpp
[NFC] Use TypeSize::geFixedValue() instead of TypeSize::getFixedSize()
2023-01-11 16:49:38 +00:00
RISCVInsertVSETVLI.cpp
[RISCV][InsertVSETVLI] Handle partially transparent instructions in PRE
2023-01-27 11:52:09 -08:00
RISCVInstrFormats.td
[RISCV] Add MC support of RISCV Zcb Extension
2023-01-26 12:54:00 -08:00
RISCVInstrFormatsC.td
[RISCV] Add MC support of RISCV Zcb Extension
2023-01-26 12:54:00 -08:00
RISCVInstrFormatsV.td
…
RISCVInstrInfo.cpp
[RISCV] Add MC support of RISCV Zcb Extension
2023-01-26 12:54:00 -08:00
RISCVInstrInfo.h
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVInstrInfo.td
[RISCV] Use custom operand parsing for FenceArg.
2023-01-30 12:31:00 -08:00
RISCVInstrInfoA.td
…
RISCVInstrInfoC.td
[RISCV] Rename CS_ALU tablegen class to CA_ALU. NFC
2023-01-25 17:08:42 -08:00
RISCVInstrInfoD.td
…
RISCVInstrInfoF.td
[RISCV] Move FRM parsing in the assembler to a custom operand parser.
2023-01-29 12:25:00 -08:00
RISCVInstrInfoM.td
…
RISCVInstrInfoV.td
…
RISCVInstrInfoVPseudos.td
[RISCV] Combine FP_TO_INT to vfwcvt/fvncvt
2023-01-24 09:44:57 +00:00
RISCVInstrInfoVSDPatterns.td
[RISCV][NFC] Rename narrowing patterns to use W suffix
2023-01-26 11:17:14 +00:00
RISCVInstrInfoVVLPatterns.td
[RISCV][NFC] Rename narrowing patterns to use W suffix
2023-01-26 11:17:14 +00:00
RISCVInstrInfoXTHead.td
[RISCV] Add codegen support for RISCV XTHeadVdot Extension
2023-01-10 18:12:43 +08:00
RISCVInstrInfoXVentana.td
[RISCV] Add more XVentanaCondOps patterns.
2023-01-06 08:29:23 -08:00
RISCVInstrInfoZb.td
[RISCV] Simplify predicates with llvm::countr_zero (NFC)
2023-01-28 12:14:43 -08:00
RISCVInstrInfoZc.td
[RISCV] Bump Zca, Zcb, Zcd, Zcf version to 1.0.
2023-01-28 22:04:34 -08:00
RISCVInstrInfoZfh.td
…
RISCVInstrInfoZicbo.td
…
RISCVInstrInfoZk.td
…
RISCVISelDAGToDAG.cpp
[Target] Use llvm::count{l,r}_{zero,one} (NFC)
2023-01-28 09:23:07 -08:00
RISCVISelDAGToDAG.h
[RISCV] Prefer ADDI over ORI if the known bits are disjoint.
2022-12-28 19:59:42 -08:00
RISCVISelLowering.cpp
[RISCV] Peak through BITCAST in isUsedByReturnOnly
2023-01-30 23:41:14 +00:00
RISCVISelLowering.h
[RISCV] Combine FP_TO_INT to vfwcvt/fvncvt
2023-01-24 09:44:57 +00:00
RISCVMachineFunctionInfo.cpp
…
RISCVMachineFunctionInfo.h
…
RISCVMacroFusion.cpp
…
RISCVMacroFusion.h
…
RISCVMakeCompressible.cpp
…
RISCVMCInstLower.cpp
…
RISCVMergeBaseOffset.cpp
…
RISCVProcessors.td
[RISCV] Move Processors and Features from RISCV.td to their own files.
2023-01-23 10:17:08 -08:00
RISCVRedundantCopyElimination.cpp
…
RISCVRegisterInfo.cpp
[RISCV] Remove uses of Register::isPhysicalRegister/isVirtualRegister. NFC
2023-01-11 10:07:48 -08:00
RISCVRegisterInfo.h
Recommit "[RISCV] Enable the LocalStackSlotAllocation pass support"
2023-01-06 09:54:19 -08:00
RISCVRegisterInfo.td
…
RISCVSchedRocket.td
…
RISCVSchedSiFive7.td
…
RISCVSchedSyntacoreSCR1.td
…
RISCVSchedule.td
…
RISCVScheduleV.td
…
RISCVScheduleZb.td
…
RISCVSExtWRemoval.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVStripWSuffix.cpp
[RISCV] Refactor RISCV::hasAllWUsers to hasAllNBitUsers similar to RISCVISelDAGToDAG's version. NFC
2022-12-28 12:49:23 -08:00
RISCVSubtarget.cpp
[RISCV] Use llvm::bit_floor and std::clamp (NFC)
2023-01-28 00:49:38 -08:00
RISCVSubtarget.h
[RISCV] Remove RISCVSubtarget::getArchMinVLen()/getArchMaxVLen().
2023-01-10 15:32:11 -08:00
RISCVSystemOperands.td
…
RISCVTargetMachine.cpp
[llvm] Use llvm::bit_floor instead of llvm::PowerOf2Floor (NFC)
2023-01-28 09:06:31 -08:00
RISCVTargetMachine.h
…
RISCVTargetObjectFile.cpp
…
RISCVTargetObjectFile.h
…
RISCVTargetTransformInfo.cpp
[Target] Use llvm::count{l,r}_{zero,one} (NFC)
2023-01-28 09:23:07 -08:00
RISCVTargetTransformInfo.h
[RISCV][LSR] Treat number of instructions as dominate factor in LSR cost decisions
2023-01-24 11:42:37 -08:00