a9871772a8
This matches the behavior from a number of other targets, including e.g. X86. This does have the effect of increasing register pressure slightly, but we have a relative abundance of registers in the ISA compared to other targets which use the same heuristic. The motivation here is that our current cost heuristic treats number of registers as the dominant cost. As a result, an extra use outside of a loop can radically change the LSR result. As an example consider test4 from the recently added test/Transforms/LoopStrengthReduce/RISCV/lsr-cost-compare.ll. Without a use outside the loop (see test3), we convert the IV into a pointer increment. With one, we leave the gep in place. The pointer increment version both decreases number of instructions in some loops, and creates parallel chains of computation (i.e. decreases critical path depth). Both are generally profitable. Arguably, we should really be using a more sophisticated model here - such as e.g. using profile information or explicitly modeling parallelism gains. However, as a practical matter starting with the same mild hack that other targets have used seems reasonable. Differential Revision: https://reviews.llvm.org/D142227
347 lines
14 KiB
C++
347 lines
14 KiB
C++
//===- RISCVTargetTransformInfo.h - RISC-V specific TTI ---------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file defines a TargetTransformInfo::Concept conforming object specific
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/// to the RISC-V target machine. It uses the target's detailed information to
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/// provide more precise answers to certain TTI queries, while letting the
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/// target independent and default TTI implementations handle the rest.
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///
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#define LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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#include "RISCVSubtarget.h"
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#include "RISCVTargetMachine.h"
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#include "llvm/Analysis/IVDescriptors.h"
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#include "llvm/Analysis/TargetTransformInfo.h"
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#include "llvm/CodeGen/BasicTTIImpl.h"
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#include "llvm/IR/Function.h"
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#include <optional>
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namespace llvm {
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class RISCVTTIImpl : public BasicTTIImplBase<RISCVTTIImpl> {
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using BaseT = BasicTTIImplBase<RISCVTTIImpl>;
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using TTI = TargetTransformInfo;
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friend BaseT;
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const RISCVSubtarget *ST;
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const RISCVTargetLowering *TLI;
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const RISCVSubtarget *getST() const { return ST; }
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const RISCVTargetLowering *getTLI() const { return TLI; }
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/// This function returns an estimate for VL to be used in VL based terms
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/// of the cost model. For fixed length vectors, this is simply the
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/// vector length. For scalable vectors, we return results consistent
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/// with getVScaleForTuning under the assumption that clients are also
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/// using that when comparing costs between scalar and vector representation.
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/// This does unfortunately mean that we can both undershoot and overshot
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/// the true cost significantly if getVScaleForTuning is wildly off for the
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/// actual target hardware.
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unsigned getEstimatedVLFor(VectorType *Ty);
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/// Return the cost of LMUL. The larger the LMUL, the higher the cost.
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InstructionCost getLMULCost(MVT VT);
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public:
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explicit RISCVTTIImpl(const RISCVTargetMachine *TM, const Function &F)
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: BaseT(TM, F.getParent()->getDataLayout()), ST(TM->getSubtargetImpl(F)),
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TLI(ST->getTargetLowering()) {}
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/// Return the cost of materializing an immediate for a value operand of
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/// a store instruction.
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InstructionCost getStoreImmCost(Type *VecTy, TTI::OperandValueInfo OpInfo,
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TTI::TargetCostKind CostKind);
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InstructionCost getIntImmCost(const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind);
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InstructionCost getIntImmCostInst(unsigned Opcode, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind,
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Instruction *Inst = nullptr);
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InstructionCost getIntImmCostIntrin(Intrinsic::ID IID, unsigned Idx,
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const APInt &Imm, Type *Ty,
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TTI::TargetCostKind CostKind);
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TargetTransformInfo::PopcntSupportKind getPopcntSupport(unsigned TyWidth);
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bool shouldExpandReduction(const IntrinsicInst *II) const;
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bool supportsScalableVectors() const { return ST->hasVInstructions(); }
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bool enableScalableVectorization() const { return ST->hasVInstructions(); }
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PredicationStyle emitGetActiveLaneMask() const {
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return ST->hasVInstructions() ? PredicationStyle::Data
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: PredicationStyle::None;
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}
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std::optional<unsigned> getMaxVScale() const;
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std::optional<unsigned> getVScaleForTuning() const;
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TypeSize getRegisterBitWidth(TargetTransformInfo::RegisterKind K) const;
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unsigned getRegUsageForType(Type *Ty);
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unsigned getMaximumVF(unsigned ElemWidth, unsigned Opcode) const;
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bool preferEpilogueVectorization() const {
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// Epilogue vectorization is usually unprofitable - tail folding or
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// a smaller VF would have been better. This a blunt hammer - we
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// should re-examine this once vectorization is better tuned.
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return false;
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}
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InstructionCost getMaskedMemoryOpCost(unsigned Opcode, Type *Src,
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Align Alignment, unsigned AddressSpace,
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TTI::TargetCostKind CostKind);
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void getUnrollingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::UnrollingPreferences &UP,
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OptimizationRemarkEmitter *ORE);
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void getPeelingPreferences(Loop *L, ScalarEvolution &SE,
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TTI::PeelingPreferences &PP);
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unsigned getMinVectorRegisterBitWidth() const {
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return ST->useRVVForFixedLengthVectors() ? 16 : 0;
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}
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InstructionCost getSpliceCost(VectorType *Tp, int Index);
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InstructionCost getShuffleCost(TTI::ShuffleKind Kind, VectorType *Tp,
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ArrayRef<int> Mask,
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TTI::TargetCostKind CostKind, int Index,
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VectorType *SubTp,
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ArrayRef<const Value *> Args = std::nullopt);
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InstructionCost getIntrinsicInstrCost(const IntrinsicCostAttributes &ICA,
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TTI::TargetCostKind CostKind);
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InstructionCost getGatherScatterOpCost(unsigned Opcode, Type *DataTy,
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const Value *Ptr, bool VariableMask,
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Align Alignment,
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TTI::TargetCostKind CostKind,
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const Instruction *I);
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InstructionCost getCastInstrCost(unsigned Opcode, Type *Dst, Type *Src,
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TTI::CastContextHint CCH,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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InstructionCost getMinMaxReductionCost(VectorType *Ty, VectorType *CondTy,
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bool IsUnsigned,
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TTI::TargetCostKind CostKind);
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InstructionCost getArithmeticReductionCost(unsigned Opcode, VectorType *Ty,
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std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind);
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InstructionCost getExtendedReductionCost(unsigned Opcode, bool IsUnsigned,
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Type *ResTy, VectorType *ValTy,
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std::optional<FastMathFlags> FMF,
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TTI::TargetCostKind CostKind);
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InstructionCost
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getMemoryOpCost(unsigned Opcode, Type *Src, MaybeAlign Alignment,
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unsigned AddressSpace, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo OpdInfo = {TTI::OK_AnyValue, TTI::OP_None},
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const Instruction *I = nullptr);
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InstructionCost getCmpSelInstrCost(unsigned Opcode, Type *ValTy, Type *CondTy,
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CmpInst::Predicate VecPred,
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TTI::TargetCostKind CostKind,
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const Instruction *I = nullptr);
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using BaseT::getVectorInstrCost;
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InstructionCost getVectorInstrCost(unsigned Opcode, Type *Val,
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TTI::TargetCostKind CostKind,
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unsigned Index, Value *Op0, Value *Op1);
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InstructionCost getArithmeticInstrCost(
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unsigned Opcode, Type *Ty, TTI::TargetCostKind CostKind,
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TTI::OperandValueInfo Op1Info = {TTI::OK_AnyValue, TTI::OP_None},
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TTI::OperandValueInfo Op2Info = {TTI::OK_AnyValue, TTI::OP_None},
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ArrayRef<const Value *> Args = ArrayRef<const Value *>(),
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const Instruction *CxtI = nullptr);
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bool isElementTypeLegalForScalableVector(Type *Ty) const {
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return TLI->isLegalElementTypeForRVV(Ty);
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}
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bool isLegalMaskedLoadStore(Type *DataType, Align Alignment) {
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if (!ST->hasVInstructions())
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return false;
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// Only support fixed vectors if we know the minimum vector size.
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if (isa<FixedVectorType>(DataType) && !ST->useRVVForFixedLengthVectors())
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return false;
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// Don't allow elements larger than the ELEN.
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// FIXME: How to limit for scalable vectors?
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if (isa<FixedVectorType>(DataType) &&
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DataType->getScalarSizeInBits() > ST->getELEN())
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return false;
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if (Alignment <
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DL.getTypeStoreSize(DataType->getScalarType()).getFixedValue())
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return false;
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return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
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}
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bool isLegalMaskedLoad(Type *DataType, Align Alignment) {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedStore(Type *DataType, Align Alignment) {
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return isLegalMaskedLoadStore(DataType, Alignment);
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}
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bool isLegalMaskedGatherScatter(Type *DataType, Align Alignment) {
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if (!ST->hasVInstructions())
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return false;
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// Only support fixed vectors if we know the minimum vector size.
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if (isa<FixedVectorType>(DataType) && !ST->useRVVForFixedLengthVectors())
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return false;
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// Don't allow elements larger than the ELEN.
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// FIXME: How to limit for scalable vectors?
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if (isa<FixedVectorType>(DataType) &&
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DataType->getScalarSizeInBits() > ST->getELEN())
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return false;
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if (Alignment <
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DL.getTypeStoreSize(DataType->getScalarType()).getFixedValue())
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return false;
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return TLI->isLegalElementTypeForRVV(DataType->getScalarType());
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}
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bool isLegalMaskedGather(Type *DataType, Align Alignment) {
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return isLegalMaskedGatherScatter(DataType, Alignment);
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}
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bool isLegalMaskedScatter(Type *DataType, Align Alignment) {
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return isLegalMaskedGatherScatter(DataType, Alignment);
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}
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bool forceScalarizeMaskedGather(VectorType *VTy, Align Alignment) {
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// Scalarize masked gather for RV64 if EEW=64 indices aren't supported.
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return ST->is64Bit() && !ST->hasVInstructionsI64();
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}
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bool forceScalarizeMaskedScatter(VectorType *VTy, Align Alignment) {
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// Scalarize masked scatter for RV64 if EEW=64 indices aren't supported.
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return ST->is64Bit() && !ST->hasVInstructionsI64();
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}
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/// \returns How the target needs this vector-predicated operation to be
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/// transformed.
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TargetTransformInfo::VPLegalization
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getVPLegalizationStrategy(const VPIntrinsic &PI) const {
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using VPLegalization = TargetTransformInfo::VPLegalization;
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if (!ST->hasVInstructions() ||
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(PI.getIntrinsicID() == Intrinsic::vp_reduce_mul &&
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cast<VectorType>(PI.getArgOperand(1)->getType())
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->getElementType()
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->getIntegerBitWidth() != 1))
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return VPLegalization(VPLegalization::Discard, VPLegalization::Convert);
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return VPLegalization(VPLegalization::Legal, VPLegalization::Legal);
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}
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bool isLegalToVectorizeReduction(const RecurrenceDescriptor &RdxDesc,
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ElementCount VF) const {
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if (!VF.isScalable())
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return true;
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Type *Ty = RdxDesc.getRecurrenceType();
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if (!TLI->isLegalElementTypeForRVV(Ty))
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return false;
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switch (RdxDesc.getRecurrenceKind()) {
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case RecurKind::Add:
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case RecurKind::FAdd:
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case RecurKind::And:
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case RecurKind::Or:
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case RecurKind::Xor:
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case RecurKind::SMin:
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case RecurKind::SMax:
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case RecurKind::UMin:
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case RecurKind::UMax:
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case RecurKind::FMin:
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case RecurKind::FMax:
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case RecurKind::SelectICmp:
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case RecurKind::SelectFCmp:
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case RecurKind::FMulAdd:
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return true;
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default:
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return false;
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}
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}
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unsigned getMaxInterleaveFactor(unsigned VF) {
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// If the loop will not be vectorized, don't interleave the loop.
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// Let regular unroll to unroll the loop.
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return VF == 1 ? 1 : ST->getMaxInterleaveFactor();
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}
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enum RISCVRegisterClass { GPRRC, FPRRC, VRRC };
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unsigned getNumberOfRegisters(unsigned ClassID) const {
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switch (ClassID) {
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case RISCVRegisterClass::GPRRC:
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// 31 = 32 GPR - x0 (zero register)
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// FIXME: Should we exclude fixed registers like SP, TP or GP?
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return 31;
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case RISCVRegisterClass::FPRRC:
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if (ST->hasStdExtF())
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return 32;
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return 0;
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case RISCVRegisterClass::VRRC:
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// Although there are 32 vector registers, v0 is special in that it is the
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// only register that can be used to hold a mask.
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// FIXME: Should we conservatively return 31 as the number of usable
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// vector registers?
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return ST->hasVInstructions() ? 32 : 0;
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}
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llvm_unreachable("unknown register class");
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}
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unsigned getRegisterClassForType(bool Vector, Type *Ty = nullptr) const {
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if (Vector)
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return RISCVRegisterClass::VRRC;
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if (!Ty)
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return RISCVRegisterClass::GPRRC;
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Type *ScalarTy = Ty->getScalarType();
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if ((ScalarTy->isHalfTy() && ST->hasStdExtZfhOrZfhmin()) ||
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(ScalarTy->isFloatTy() && ST->hasStdExtF()) ||
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(ScalarTy->isDoubleTy() && ST->hasStdExtD())) {
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return RISCVRegisterClass::FPRRC;
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}
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return RISCVRegisterClass::GPRRC;
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}
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const char *getRegisterClassName(unsigned ClassID) const {
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switch (ClassID) {
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case RISCVRegisterClass::GPRRC:
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return "RISCV::GPRRC";
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case RISCVRegisterClass::FPRRC:
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return "RISCV::FPRRC";
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case RISCVRegisterClass::VRRC:
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return "RISCV::VRRC";
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}
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llvm_unreachable("unknown register class");
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}
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bool isLSRCostLess(const TargetTransformInfo::LSRCost &C1,
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const TargetTransformInfo::LSRCost &C2);
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};
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} // end namespace llvm
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#endif // LLVM_LIB_TARGET_RISCV_RISCVTARGETTRANSFORMINFO_H
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