Files
clang-p2996/llvm/test/CodeGen/MIR/ARM/nested-instruction-bundle-error.mir
Puyan Lotfi 43e94b15ea Followup on Proposal to move MIR physical register namespace to '$' sigil.
Discussed here:

http://lists.llvm.org/pipermail/llvm-dev/2018-January/120320.html

In preparation for adding support for named vregs we are changing the sigil for
physical registers in MIR to '$' from '%'. This will prevent name clashes of
named physical register with named vregs.

llvm-svn: 323922
2018-01-31 22:04:26 +00:00

31 lines
763 B
YAML

# RUN: not llc -mtriple thumbv7-apple-ios -run-pass none -o /dev/null %s 2>&1 | FileCheck %s
--- |
define i32 @test1(i32 %a) {
entry:
%cmp = icmp sgt i32 %a, -78
%. = zext i1 %cmp to i32
ret i32 %.
}
...
---
name: test1
tracksRegLiveness: true
liveins:
- { reg: '$r0' }
body: |
bb.0.entry:
liveins: $r0
$r1 = t2MOVi 0, 14, _, _
t2CMNri killed $r0, 78, 14, _, implicit-def $cpsr
BUNDLE implicit-def dead $itstate, implicit-def $r1, implicit killed $cpsr {
t2IT 12, 8, implicit-def $itstate
$r1 = t2MOVi 1, 12, killed $cpsr, _
; CHECK: [[@LINE+1]]:14: nested instruction bundles are not allowed
BUNDLE {
}
}
$r0 = tMOVr killed $r1, 14, _
tBX_RET 14, _, implicit killed $r0
...