Files
clang-p2996/llvm/test/CodeGen/MSP430/jumptable.ll
Alexander Richardson 8f44579d0b Emit a left-shift instead of a power-of-two multiply for jump-tables
Summary:
SelectionDAGLegalize::ExpandNode() inserts an ISD::MUL when lowering a
BR_JT opcode. While many backends optimize this multiply into a shift, e.g.
the MIPS backend currently always lowers this into a sequence of
load-immediate+multiply+mflo in MipsSETargetLowering::lowerMulDiv().

I initially changed the multiply to a shift in the MIPS backend but it
turns out that would not have handled the MIPSR6 case and was a lot more
code than doing it in LegalizeDAG.
I believe performing this simple optimization in LegalizeDAG instead of
each individual backend is the better solution since this also fixes other
backeds such as MSP430 which calls the multiply runtime function
__mspabi_mpyi without this patch.

Reviewers: sdardis, atanasyan, pftbest, asl

Reviewed By: sdardis

Subscribers: llvm-commits

Differential Revision: https://reviews.llvm.org/D45760

llvm-svn: 332439
2018-05-16 08:58:26 +00:00

58 lines
1.5 KiB
LLVM

; RUN: llc < %s | FileCheck %s
target datalayout = "e-p:16:16:16-i8:8:8-i16:16:16-i32:16:32-n8:16"
target triple = "msp430---elf"
; Function Attrs: nounwind
define i16 @test(i16 %i) #0 {
entry:
; CHECK-LABEL: test:
; CHECK: sub.w #4, r1
; CHECK-NEXT: mov.w r12, 0(r1)
; CHECK-NEXT: cmp.w #4, r12
; CHECK-NEXT: jhs .LBB0_3
%retval = alloca i16, align 2
%i.addr = alloca i16, align 2
store i16 %i, i16* %i.addr, align 2
%0 = load i16, i16* %i.addr, align 2
; CHECK: rla.w r12
; CHECK-NEXT: br .LJTI0_0(r12)
switch i16 %0, label %sw.default [
i16 0, label %sw.bb
i16 1, label %sw.bb1
i16 2, label %sw.bb2
i16 3, label %sw.bb3
]
sw.bb: ; preds = %entry
store i16 0, i16* %retval
br label %return
sw.bb1: ; preds = %entry
store i16 1, i16* %retval
br label %return
sw.bb2: ; preds = %entry
store i16 2, i16* %retval
br label %return
sw.bb3: ; preds = %entry
store i16 3, i16* %retval
br label %return
sw.default: ; preds = %entry
store i16 2, i16* %retval
br label %return
return: ; preds = %sw.default, %sw.bb3, %sw.bb2, %sw.bb1, %sw.bb
%1 = load i16, i16* %retval
ret i16 %1
; CHECK: ret
}
; CHECK: .LJTI0_0:
; CHECK-NEXT: .short .LBB0_2
; CHECK-NEXT: .short .LBB0_4
; CHECK-NEXT: .short .LBB0_3
; CHECK-NEXT: .short .LBB0_5