0bd4d8c901
Support G_LSHR/G_ASHR/G_SHL. We have 3 variance for
shift instructions : shift gpr, shift imm, shift 1.
Currently GlobalIsel TableGen generate patterns for
shift imm and shift 1, but with shiftCount i8.
In G_LSHR/G_ASHR/G_SHL like LLVM-IR both arguments
has the same type, so for now only shift i8 can use
auto generated TableGen patterns.
The support of G_SHL/G_ASHR enables tryCombineSExt
from LegalizationArtifactCombiner.h to hit, which
results in different legalization for the following tests:
LLVM :: CodeGen/X86/GlobalISel/ext-x86-64.ll
LLVM :: CodeGen/X86/GlobalISel/gep.ll
LLVM :: CodeGen/X86/GlobalISel/legalize-ext-x86-64.mir
-; X64-NEXT: movsbl %dil, %eax
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: shll %cl, %edi
+; X64-NEXT: movl $24, %ecx
+; X64-NEXT: # kill: def $cl killed $ecx
+; X64-NEXT: sarl %cl, %edi
+; X64-NEXT: movl %edi, %eax
..which is not optimal and should be addressed later.
Rework of the patch by igorb
Reviewed By: igorb
Differential Revision: https://reviews.llvm.org/D44395
llvm-svn: 327499
126 lines
3.1 KiB
LLVM
126 lines
3.1 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=x86_64-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X64
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; RUN: llc -mtriple=i386-linux-gnu -global-isel -verify-machineinstrs < %s -o - | FileCheck %s --check-prefix=X32
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define i8 @test_zext_i1toi8(i32 %a) {
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; X64-LABEL: test_zext_i1toi8:
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; X64: # %bb.0:
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; X64-NEXT: andb $1, %dil
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_zext_i1toi8:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andb $1, %al
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; X32-NEXT: # kill: def $al killed $al killed $eax
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; X32-NEXT: retl
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%val = trunc i32 %a to i1
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%r = zext i1 %val to i8
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ret i8 %r
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}
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define i16 @test_zext_i1toi16(i32 %a) {
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; X64-LABEL: test_zext_i1toi16:
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; X64: # %bb.0:
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; X64-NEXT: andw $1, %di
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_zext_i1toi16:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andw $1, %ax
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; X32-NEXT: # kill: def $ax killed $ax killed $eax
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; X32-NEXT: retl
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%val = trunc i32 %a to i1
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%r = zext i1 %val to i16
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ret i16 %r
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}
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define i32 @test_zext_i1(i32 %a) {
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; X64-LABEL: test_zext_i1:
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; X64: # %bb.0:
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; X64-NEXT: andl $1, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_zext_i1:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: andl $1, %eax
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; X32-NEXT: retl
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%val = trunc i32 %a to i1
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%r = zext i1 %val to i32
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ret i32 %r
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}
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define i32 @test_zext_i8(i8 %val) {
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; X64-LABEL: test_zext_i8:
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; X64: # %bb.0:
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; X64-NEXT: movzbl %dil, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_zext_i8:
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; X32: # %bb.0:
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; X32-NEXT: movzbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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%r = zext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_zext_i16(i16 %val) {
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; X64-LABEL: test_zext_i16:
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; X64: # %bb.0:
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; X64-NEXT: movzwl %di, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_zext_i16:
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; X32: # %bb.0:
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; X32-NEXT: movzwl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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%r = zext i16 %val to i32
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ret i32 %r
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}
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define i32 @test_sext_i8(i8 %val) {
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; X64-LABEL: test_sext_i8:
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; X64: # %bb.0:
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; X64-NEXT: movl $24, %ecx
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; X64-NEXT: # kill: def $cl killed $ecx
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; X64-NEXT: shll %cl, %edi
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; X64-NEXT: movl $24, %ecx
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; X64-NEXT: # kill: def $cl killed $ecx
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; X64-NEXT: sarl %cl, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_sext_i8:
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; X32: # %bb.0:
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; X32-NEXT: movsbl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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%r = sext i8 %val to i32
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ret i32 %r
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}
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define i32 @test_sext_i16(i16 %val) {
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; X64-LABEL: test_sext_i16:
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; X64: # %bb.0:
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; X64-NEXT: movl $16, %ecx
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; X64-NEXT: # kill: def $cl killed $ecx
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; X64-NEXT: shll %cl, %edi
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; X64-NEXT: movl $16, %ecx
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; X64-NEXT: # kill: def $cl killed $ecx
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; X64-NEXT: sarl %cl, %edi
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; X64-NEXT: movl %edi, %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: test_sext_i16:
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; X32: # %bb.0:
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; X32-NEXT: movswl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: retl
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%r = sext i16 %val to i32
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ret i32 %r
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}
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