d7391eefdf
At one point in time acquire implied mayLoad and mayStore as did release. Thus we needed separate pseudos that also carried that property. This appears to no longer be the case. I believe it was changed in 2012 with a comment saying that atomic memory accesses are marked volatile which preserves the ordering. So from what I can tell we shouldn't need additional pseudos since they aren't carry any flags that are different from the normal instructions. The only thing I can think of is that we may consider them for load folding candidates in the peephole pass now where we didn't before. If that's important hopefully there's something in the memory operand we can check to prevent the folding without relying on pseudo instructions. Differential Revision: https://reviews.llvm.org/D50212 llvm-svn: 338925
167 lines
4.6 KiB
LLVM
167 lines
4.6 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-- -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X64
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; RUN: llc < %s -mtriple=i686-- -mattr=+sse2 -verify-machineinstrs | FileCheck %s --check-prefix=CHECK --check-prefix=X32
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; On x86, an atomic rmw operation that does not modify the value in memory
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; (such as atomic add 0) can be replaced by an mfence followed by a mov.
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; This is explained (with the motivation for such an optimization) in
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; http://www.hpl.hp.com/techreports/2012/HPL-2012-68.pdf
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define i8 @add8(i8* %p) {
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; X64-LABEL: add8:
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; X64: # %bb.0:
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; X64-NEXT: mfence
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; X64-NEXT: movb (%rdi), %al
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; X64-NEXT: retq
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;
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; X32-LABEL: add8:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: mfence
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; X32-NEXT: movb (%eax), %al
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; X32-NEXT: retl
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%1 = atomicrmw add i8* %p, i8 0 monotonic
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ret i8 %1
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}
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define i16 @or16(i16* %p) {
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; X64-LABEL: or16:
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; X64: # %bb.0:
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; X64-NEXT: mfence
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; X64-NEXT: movzwl (%rdi), %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: or16:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: mfence
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; X32-NEXT: movzwl (%eax), %eax
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; X32-NEXT: retl
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%1 = atomicrmw or i16* %p, i16 0 acquire
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ret i16 %1
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}
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define i32 @xor32(i32* %p) {
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; X64-LABEL: xor32:
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; X64: # %bb.0:
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; X64-NEXT: mfence
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: xor32:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: mfence
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; X32-NEXT: movl (%eax), %eax
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; X32-NEXT: retl
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%1 = atomicrmw xor i32* %p, i32 0 release
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ret i32 %1
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}
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define i64 @sub64(i64* %p) {
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; X64-LABEL: sub64:
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; X64: # %bb.0:
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; X64-NEXT: mfence
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; X64-NEXT: movq (%rdi), %rax
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; X64-NEXT: retq
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;
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; X32-LABEL: sub64:
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; X32: # %bb.0:
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; X32-NEXT: pushl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: pushl %esi
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; X32-NEXT: .cfi_def_cfa_offset 12
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; X32-NEXT: .cfi_offset %esi, -12
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; X32-NEXT: .cfi_offset %ebx, -8
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; X32-NEXT: movl {{[0-9]+}}(%esp), %esi
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; X32-NEXT: movl (%esi), %eax
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; X32-NEXT: movl 4(%esi), %edx
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; X32-NEXT: .p2align 4, 0x90
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; X32-NEXT: .LBB3_1: # %atomicrmw.start
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; X32-NEXT: # =>This Inner Loop Header: Depth=1
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; X32-NEXT: movl %edx, %ecx
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; X32-NEXT: movl %eax, %ebx
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; X32-NEXT: lock cmpxchg8b (%esi)
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; X32-NEXT: jne .LBB3_1
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; X32-NEXT: # %bb.2: # %atomicrmw.end
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; X32-NEXT: popl %esi
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: popl %ebx
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; X32-NEXT: .cfi_def_cfa_offset 4
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; X32-NEXT: retl
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%1 = atomicrmw sub i64* %p, i64 0 seq_cst
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ret i64 %1
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}
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define i128 @or128(i128* %p) {
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; X64-LABEL: or128:
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; X64: # %bb.0:
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; X64-NEXT: pushq %rax
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; X64-NEXT: .cfi_def_cfa_offset 16
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; X64-NEXT: xorl %esi, %esi
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; X64-NEXT: xorl %edx, %edx
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; X64-NEXT: callq __sync_fetch_and_or_16
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; X64-NEXT: popq %rcx
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; X64-NEXT: .cfi_def_cfa_offset 8
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; X64-NEXT: retq
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;
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; X32-LABEL: or128:
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; X32: # %bb.0:
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; X32-NEXT: pushl %ebp
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; X32-NEXT: .cfi_def_cfa_offset 8
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; X32-NEXT: .cfi_offset %ebp, -8
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; X32-NEXT: movl %esp, %ebp
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; X32-NEXT: .cfi_def_cfa_register %ebp
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; X32-NEXT: pushl %edi
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; X32-NEXT: pushl %esi
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; X32-NEXT: andl $-8, %esp
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; X32-NEXT: subl $16, %esp
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; X32-NEXT: .cfi_offset %esi, -16
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; X32-NEXT: .cfi_offset %edi, -12
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; X32-NEXT: movl 8(%ebp), %esi
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; X32-NEXT: movl %esp, %eax
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl $0
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; X32-NEXT: pushl 12(%ebp)
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; X32-NEXT: pushl %eax
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; X32-NEXT: calll __sync_fetch_and_or_16
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; X32-NEXT: addl $20, %esp
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; X32-NEXT: movl (%esp), %eax
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; X32-NEXT: movl {{[0-9]+}}(%esp), %ecx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edx
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; X32-NEXT: movl {{[0-9]+}}(%esp), %edi
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; X32-NEXT: movl %edi, 12(%esi)
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; X32-NEXT: movl %edx, 8(%esi)
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; X32-NEXT: movl %ecx, 4(%esi)
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; X32-NEXT: movl %eax, (%esi)
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; X32-NEXT: movl %esi, %eax
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; X32-NEXT: leal -8(%ebp), %esp
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; X32-NEXT: popl %esi
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; X32-NEXT: popl %edi
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; X32-NEXT: popl %ebp
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; X32-NEXT: .cfi_def_cfa %esp, 4
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; X32-NEXT: retl $4
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%1 = atomicrmw or i128* %p, i128 0 monotonic
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ret i128 %1
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}
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; For 'and', the idempotent value is (-1)
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define i32 @and32 (i32* %p) {
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; X64-LABEL: and32:
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; X64: # %bb.0:
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; X64-NEXT: mfence
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; X64-NEXT: movl (%rdi), %eax
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; X64-NEXT: retq
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;
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; X32-LABEL: and32:
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; X32: # %bb.0:
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; X32-NEXT: movl {{[0-9]+}}(%esp), %eax
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; X32-NEXT: mfence
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; X32-NEXT: movl (%eax), %eax
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; X32-NEXT: retl
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%1 = atomicrmw and i32* %p, i32 -1 acq_rel
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ret i32 %1
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}
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