8a83f16ccd
As mentioned on D44647, this patch increases the default memory latency to +5cy , which more closely matches what most custom cases are doing for reg-mem instructions. I've bumped LoadLatency, ReadAfterLd and WriteLoad values to 5cy to be consistent. As Sandy Bridge is currently our default generic model, this affects a lot of scheduling tests... Differential Revision: https://reviews.llvm.org/D44654 llvm-svn: 329388
19 lines
715 B
LLVM
19 lines
715 B
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=x86-64 -mattr=+clwb | FileCheck %s --check-prefix=GENERIC
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; RUN: llc < %s -mtriple=x86_64-unknown-unknown -print-schedule -mcpu=skx | FileCheck %s --check-prefix=SKX
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define void @clwb(i8* %a0) nounwind {
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; GENERIC-LABEL: clwb:
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; GENERIC: # %bb.0:
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; GENERIC-NEXT: clwb (%rdi) # sched: [5:0.50]
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; GENERIC-NEXT: retq # sched: [1:1.00]
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;
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; SKX-LABEL: clwb:
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; SKX: # %bb.0:
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; SKX-NEXT: clwb (%rdi) # sched: [5:0.50]
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; SKX-NEXT: retq # sched: [7:1.00]
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tail call void @llvm.x86.clwb(i8* %a0)
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ret void
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}
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declare void @llvm.x86.clwb(i8*) nounwind
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