9c098ed819
I removed this in r316797 because the coverage report showed no coverage and I thought it should have been handled by the auto generated table. I now see that there is code that bypasses the table if the shift amount is out of bounds. This adds back the code. We'll codegen out of bounds i8 shifts to effectively (amount & 0x1f). The 0x1f is a strange quirk of x86 that shift amounts are always masked to 5-bits(except 64-bits). So if the masked value is still out bounds the result will be 0. Fixes PR36731. llvm-svn: 327540
396 lines
8.8 KiB
LLVM
396 lines
8.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -fast-isel -fast-isel-abort=1 -mtriple=x86_64-apple-darwin10 | FileCheck %s
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define i8 @shl_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: shl_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: shlb %cl, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i8 %a, %b
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ret i8 %c
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}
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define i16 @shl_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: shl_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $cx
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; CHECK-NEXT: shlw %cl, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i16 %a, %b
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ret i16 %c
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}
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define i32 @shl_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: shl_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $ecx
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; CHECK-NEXT: shll %cl, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i32 %a, %b
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ret i32 %c
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}
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define i64 @shl_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: shl_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rsi, %rcx
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; CHECK-NEXT: ## kill: def $cl killed $rcx
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; CHECK-NEXT: shlq %cl, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = shl i64 %a, %b
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ret i64 %c
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}
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define i8 @lshr_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: lshr_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: shrb %cl, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i8 %a, %b
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ret i8 %c
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}
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define i16 @lshr_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: lshr_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $cx
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; CHECK-NEXT: shrw %cl, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i16 %a, %b
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ret i16 %c
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}
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define i32 @lshr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: lshr_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $ecx
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; CHECK-NEXT: shrl %cl, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i32 %a, %b
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ret i32 %c
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}
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define i64 @lshr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: lshr_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rsi, %rcx
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; CHECK-NEXT: ## kill: def $cl killed $rcx
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; CHECK-NEXT: shrq %cl, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = lshr i64 %a, %b
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ret i64 %c
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}
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define i8 @ashr_i8(i8 %a, i8 %b) {
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; CHECK-LABEL: ashr_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: sarb %cl, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i8 %a, %b
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ret i8 %c
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}
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define i16 @ashr_i16(i16 %a, i16 %b) {
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; CHECK-LABEL: ashr_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $cx
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; CHECK-NEXT: sarw %cl, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i16 %a, %b
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ret i16 %c
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}
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define i32 @ashr_i32(i32 %a, i32 %b) {
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; CHECK-LABEL: ashr_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movl %esi, %ecx
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; CHECK-NEXT: ## kill: def $cl killed $ecx
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; CHECK-NEXT: sarl %cl, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i32 %a, %b
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ret i32 %c
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}
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define i64 @ashr_i64(i64 %a, i64 %b) {
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; CHECK-LABEL: ashr_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movq %rsi, %rcx
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; CHECK-NEXT: ## kill: def $cl killed $rcx
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; CHECK-NEXT: sarq %cl, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = ashr i64 %a, %b
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ret i64 %c
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}
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define i8 @shl_imm1_i8(i8 %a) {
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; CHECK-LABEL: shl_imm1_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shlb $1, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i8 %a, 1
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ret i8 %c
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}
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define i16 @shl_imm1_i16(i16 %a) {
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; CHECK-LABEL: shl_imm1_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: leal (,%rdi,2), %eax
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; CHECK-NEXT: ## kill: def $ax killed $ax killed $eax
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; CHECK-NEXT: retq
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%c = shl i16 %a, 1
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ret i16 %c
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}
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define i32 @shl_imm1_i32(i32 %a) {
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; CHECK-LABEL: shl_imm1_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: ## kill: def $edi killed $edi def $rdi
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; CHECK-NEXT: leal (,%rdi,2), %eax
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; CHECK-NEXT: retq
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%c = shl i32 %a, 1
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ret i32 %c
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}
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define i64 @shl_imm1_i64(i64 %a) {
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; CHECK-LABEL: shl_imm1_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: leaq (,%rdi,2), %rax
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; CHECK-NEXT: retq
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%c = shl i64 %a, 1
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ret i64 %c
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}
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define i8 @lshr_imm1_i8(i8 %a) {
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; CHECK-LABEL: lshr_imm1_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrb $1, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i8 %a, 1
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ret i8 %c
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}
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define i16 @lshr_imm1_i16(i16 %a) {
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; CHECK-LABEL: lshr_imm1_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrw $1, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i16 %a, 1
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ret i16 %c
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}
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define i32 @lshr_imm1_i32(i32 %a) {
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; CHECK-LABEL: lshr_imm1_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrl $1, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i32 %a, 1
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ret i32 %c
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}
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define i64 @lshr_imm1_i64(i64 %a) {
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; CHECK-LABEL: lshr_imm1_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrq $1, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = lshr i64 %a, 1
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ret i64 %c
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}
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define i8 @ashr_imm1_i8(i8 %a) {
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; CHECK-LABEL: ashr_imm1_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarb $1, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i8 %a, 1
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ret i8 %c
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}
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define i16 @ashr_imm1_i16(i16 %a) {
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; CHECK-LABEL: ashr_imm1_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarw $1, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i16 %a, 1
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ret i16 %c
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}
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define i32 @ashr_imm1_i32(i32 %a) {
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; CHECK-LABEL: ashr_imm1_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarl $1, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i32 %a, 1
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ret i32 %c
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}
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define i64 @ashr_imm1_i64(i64 %a) {
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; CHECK-LABEL: ashr_imm1_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarq $1, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = ashr i64 %a, 1
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ret i64 %c
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}
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define i8 @shl_imm4_i8(i8 %a) {
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; CHECK-LABEL: shl_imm4_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shlb $4, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i8 %a, 4
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ret i8 %c
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}
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define i16 @shl_imm4_i16(i16 %a) {
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; CHECK-LABEL: shl_imm4_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shlw $4, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i16 %a, 4
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ret i16 %c
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}
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define i32 @shl_imm4_i32(i32 %a) {
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; CHECK-LABEL: shl_imm4_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shll $4, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = shl i32 %a, 4
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ret i32 %c
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}
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define i64 @shl_imm4_i64(i64 %a) {
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; CHECK-LABEL: shl_imm4_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shlq $4, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = shl i64 %a, 4
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ret i64 %c
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}
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define i8 @lshr_imm4_i8(i8 %a) {
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; CHECK-LABEL: lshr_imm4_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrb $4, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i8 %a, 4
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ret i8 %c
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}
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define i16 @lshr_imm4_i16(i16 %a) {
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; CHECK-LABEL: lshr_imm4_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrw $4, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i16 %a, 4
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ret i16 %c
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}
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define i32 @lshr_imm4_i32(i32 %a) {
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; CHECK-LABEL: lshr_imm4_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrl $4, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = lshr i32 %a, 4
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ret i32 %c
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}
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define i64 @lshr_imm4_i64(i64 %a) {
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; CHECK-LABEL: lshr_imm4_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: shrq $4, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = lshr i64 %a, 4
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ret i64 %c
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}
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define i8 @ashr_imm4_i8(i8 %a) {
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; CHECK-LABEL: ashr_imm4_i8:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarb $4, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i8 %a, 4
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ret i8 %c
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}
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define i16 @ashr_imm4_i16(i16 %a) {
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; CHECK-LABEL: ashr_imm4_i16:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarw $4, %di
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i16 %a, 4
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ret i16 %c
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}
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define i32 @ashr_imm4_i32(i32 %a) {
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; CHECK-LABEL: ashr_imm4_i32:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarl $4, %edi
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%c = ashr i32 %a, 4
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ret i32 %c
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}
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define i64 @ashr_imm4_i64(i64 %a) {
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; CHECK-LABEL: ashr_imm4_i64:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: sarq $4, %rdi
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; CHECK-NEXT: movq %rdi, %rax
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; CHECK-NEXT: retq
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%c = ashr i64 %a, 4
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ret i64 %c
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}
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; Make sure we don't crash on out of bounds i8 shifts.
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define i8 @PR36731(i8 %a) {
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; CHECK-LABEL: PR36731:
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; CHECK: ## %bb.0:
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; CHECK-NEXT: movb $255, %cl
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; CHECK-NEXT: shlb %cl, %dil
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; CHECK-NEXT: movl %edi, %eax
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; CHECK-NEXT: retq
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%b = shl i8 %a, -1
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ret i8 %b
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}
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